Hardware Reference
In-Depth Information
will run only code that has been ''blessed'' by a trusted software vendor. The
approach is quite flexible in that even the boot loader can be replaced, if the new
code has been properly digitally signed. This is similar to the way that Apple and
TiVo ensure that the code running on their devices is safe from mischief.
The ATmega168 contains 32 8-bit general-purpose registers, which are ac-
cessed by instructions via a 5-bit field specifying which register to use. The regis-
ters are called
R0
through
R31
. A peculiar property of the ATmega168 registers is
that they are also present in the memory space. Byte 0 of the data space is equiv-
alent to
R0
of register set 0. When an instruction changes
R0
and then later reads
out memory byte 0, it finds the new value of
R0
there. Similarly, byte 1 of memory
is
R1
and so on, up to byte 31. This arrangement is shown in Fig. 5-5.
Program memory
16383
Data memory
Application
memory
1023
Scratchpad
95
I/O memory
32
31
0
Boot loader
Registers
0
7
ITHSVNZC
0
Status register (SREG)
High
Addr 80
Stack pointer (SP)
Low
Addr 81
Figure 5-5.
On-chip register and memory organization for the ATmega168.
Directly above the 32 general-purpose registers, at memory addresses 32
through 95, are 64 bytes of memory reserved for accessing I/O device registers, in-
cluding the internal system-on-a-chip devices.
In addition to the four sets of eight registers, the ATmega168 has a small num-
ber of special-purpose registers, the most important of which are illustrated in
Fig. 5-5. The
status register
contains, from left to right, the interrupt enable bit,
the half-carry bit, the sign bit, the overflow bit, the negative flag, the zero flag, and
the carry-out bit. All of these status bits, except the interrupt enable bit, are set as a
result of arithmetic operations.
The status register
I
bit allows interrupts to be enabled or disabled globally. If
the
I
bit is 0, all interrupts are disabled. Clearing this bit makes it possible to dis-
able any further interrupts in a single instruction. Setting the bit allows any inter-
rupts currently pending to occur as well as future ones. Each device has associated
