Hardware Reference
In-Depth Information
are all equivalent, a compiler can use
R1
to hold a temporary result, but it can
equally well use
R25
. The choice of register does not matter.
On other machines, however, some of the general-purpose registers may be
somewhat special. For example, on the Core i7, there is a register called
EDX
that
can be used as a general register, but which also receives half the product in a mul-
tiplication and holds half the dividend in a division.
Even when the general-purpose registers are completely interchangeable, it is
common for the operating system or compilers to adopt conventions about how
they are used. For example, some registers may hold parameters to procedures cal-
led and others may be used as scratch registers. If a compiler puts an important
local variable in
R1
and then calls a library procedure that thinks
R1
is a scratch
register available to it, when the library procedure returns,
R1
may contain garbage.
If there are system-wide conventions on how the registers are to be used, compilers
and assembly-language programmers are advised to adhere to them to avoid trou-
ble.
In addition to the ISA-level registers visible to user programs, there are always
a substantial number of special-purpose registers available only in kernel mode.
These registers control the various caches, memory, I/O devices, and other hard-
ware features of the machine. They are used only by the operating system, so
compilers and users do not have to know about them.
One control register that is something of a kernel/user hybrid is the
flags regis-
ter
or
PSW
(
Program Status Word
). This register holds various miscellaneous
bits that are needed by the CPU. The most important bits are the
condition codes
.
These bits are set on every ALU cycle and reflect the status of the result of the
most recent operation. Typical condition code bits include
N — Set when the result was Negative.
Z — Set when the result was Zero.
V — Set when the result caused an oVerflow.
C — Set when the result caused a Carry out of the leftmost bit.
A — Set when there was a carry out of bit 3 (Auxiliary carry—see below).
P — Set when the result had even Parity.
The condition codes are important because the comparison and conditional branch
instructions (also called conditional jump instructions) use them. For example, the
CMP
instruction typically subtracts two operands and sets the condition codes
based on the difference. If the operands are equal, then the difference will be zero
and the
Z
condition code bit in the
PSW
register will be set. A subsequent
BEQ
(Branch EQual) instruction tests the
Z
bit and branches if it is set.
The
PSW
contains more than just the condition codes, but the full contents
varies from machine to machine. Typical additional fields are the machine mode
