Hardware Reference
In-Depth Information
In many designs, however, as we saw in Chap. 4, microinstructions are reordered.
Thus there is a real danger that the memory will not have the expected behavior.
The problem gets even worse on a multiprocessor, with each of multiple CPUs
sending a stream of (possibly reordered) read and write requests to shared memory.
System designers can take any one of several approaches to this problem. At
one extreme, all memory requests can be serialized, so that each one is completed
before the next is issued. This strategy hurts performance but gives the simplest
memory semantics (all operations are executed in strict program order).
At the other extreme, no guarantees of any kind are given. To force an order-
ing on memory, the program must execute a
SYNC
instruction, which blocks the is-
suing of all new memory operations until all previous ones have completed. This
design puts a great burden on the compilers because they have to understand how
the underlying microarchitecture works in detail, but it gives the hardware de-
signers the maximum freedom to optimize memory usage.
Intermediate memory models are also possible, in which the hardware auto-
matically blocks the issuing of certain memory references (e.g., those involving a
RAW or WAR dependence) but not others. While having all these peculiarities
caused by the microarchitecture be exposed to the ISA level is annoying (at least to
the compiler writers and assembly-language programmers), it is very much the
trend. This trend is caused by the underlying implementations such as micro-
instruction reordering, deep pipelines, multiple cache levels, and so on. We will
see more examples of such unnatural effects later in this chapter.
All computers have some registers visible at the ISA level. They are there to
control execution of the program, hold temporary results, and serve other purposes.
In general, the registers visible at the microarchitecture level, such as
TOS
and
MAR
in Fig. 4-1, are not visible at the ISA level. A few of them, however, such as the
program counter and stack pointer, are visible at both levels. On the other hand,
registers visible at the ISA level are always visible at the microarchitecture level
since that is where they are implemented.
ISA-level registers can be roughly divided into two categories: special-purpose
registers and general-purpose registers The special-purpose registers include things
like the program counter and stack pointer, as well as other registers with a specific
function. In contrast, the general-purpose registers are there to hold key local vari-
ables and intermediate results of calculations. Their main function is to provide
rapid access to heavily used data (basically, avoiding memory accesses). RISC
machines, with their fast CPUs and (relatively) slow memories, usually have at
least 32 general-purpose registers, and the trend in new CPU designs is to have
even more.
On some machines, the general-purpose registers are completely symmetric
and interchangeable. Each one can do anything the others can do. If the registers
