Hardware Reference
In-Depth Information
32.
Suppose that we were to change the design of the machine used in Fig. 4-43 to have 16
registers instead of 8. Then we change I6 to use
R8
as its destination. What happens in
the cycles starting at cycle 6?
33.
Normally, dependences cause trouble with pipelined CPUs. Are there any optimiza-
tions that can be done with WAW dependences that might actually improve matters?
What?
34.
Rewrite the Mic-1 interpreter but having
LV
now point to the first local variable instead
of to the link pointer.
35.
Write a simulator for a 1-way direct mapped cache. Make the number of entries and
the line size parameters of the simulation. Experiment with it and report on your find-
ings.
