Hardware Reference
In-Depth Information
the last possible drop of speed out of the hardware. The OMAP4430 has a deep
pipeline, but is further relatively simple, with in-order issue, in-order execution,
and in-order retirement. The ATmega168 is very simple, with a straightforward
single main bus to which a handful of registers and one ALU are attached.
PROBLEMS
1.
What are the four steps CPUs use to execute instructions?
2.
In Fig. 4-6, the B bus register is encoded in a 4-bit field, but the C bus is represented as
a bit map. Why?
3.
In Fig. 4-6 there is a box labeled ''High bit.'' Give a circuit diagram for it.
4.
When the
JMPC
field in a microinstruction is enabled,
MBR
is ORed with
NEXT AD-
DRESS
to form the address of the next microinstruction. Are there any circumstances
in which it makes sense to have
NEXT ADDRESS
be 0x1FF and use
JMPC
?
5.
Suppose that in the example of Fig. 4-14(a) the statement
k=5;
is added after the
if
statement. What would the new assembly code be? Assume that
the compiler is an optimizing compiler.
6.
Give two different IJVM translations for the following Java statement:
i=k+n+5;
7.
Give the Java statement that produced the following IJVM code:
ILOAD j
ILOAD n
ISUB
BIPUSH 7
ISUB
DUP
IADD
ISTORE i
8.
In the text we mentioned that when translating the statement
if (Z) goto L1; else goto L2
to binary,
L2
has to be in the bottom 256 words of the control store. Would it not be
equally possible to have
L1
at, say, 0x40 and
L2
at 0x140? Explain your answer.
9.
In the microprogram for Mic-1, in
if icmpeq3
,
MDR
is copied to
H
. A few lines later it
is subtracted from
TOS
to check for equality. Surely it is better to have one statement:
