Hardware Reference
In-Depth Information
read from the register file and run through the ALU and the results stored back into
a register, just as on more modern computers.
Our three examples are very different, yet even they exhibit a certain amount
of commonality. The Core i7 has an ancient CISC instruction set that Intel's en-
gineers would dearly love to toss into San Francisco Bay, except that doing so
would violate California's water pollution laws. The OMAP4430 is a pure RISC
design, with a lean and mean instruction set. The ATmega168 is a simple 8-bit
processor for embedded applications. Yet the heart of each of them is a set of reg-
isters and one or more ALUs that perform simple arithmetic and Boolean opera-
tions on register operands.
Despite their obvious external differences, the Core i7 and the OMAP4430
have fairly similar execution units. Both of the execution units accept micro-oper-
ations that contain an opcode, two source registers, and a destination register. Both
of them can execute a micro-operation in one cycle. Both of them have deep
pipelines, branch prediction, and split I- and D-caches.
This internal similarity is not an accident or even due to the endless job-hop-
ping by Silicon Valley engineers. As we saw with our Mic-3 and Mic-4 examples,
it is easy and natural to build a pipelined data path that takes two source registers,
runs them through an ALU, and stores the results in a register. Figure 4-34 shows
this pipeline graphically. With current technology, this is the most effective design.
The main difference between the Core i7 and the OMAP4430 is how they get
from their ISA instruction set to the execution unit. The Core i7 has to break up its
CISC instructions to get them into the three-register format needed by the execu-
tion unit. That is what the front end in Fig. 4-47 is all about—hacking big instruc-
tions into nice, neat micro-operations. The OMAP4430 does not have to do any-
thing because its native ARM instructions are already nice, neat micro-operations.
This is why most new ISAs are of the RISC type—to provide a better match be-
tween the ISA instruction set and the internal execution engine.
It is instructive to compare our final design, the Mic-4, to these two real-world
examples. The Mic-4 is most like the Core i7. Both of them have the job of inter-
preting a non-RISC ISA instruction set. Both of them do this by breaking the ISA
instructions into micro-operations with an opcode, two source registers, and a dest-
ination register. In both cases, the micro-operations are deposited in a queue for
execution later. The Mic-4 has a strict in-order issue, in-order execute, in-order
retire design, whereas the Core i7 has an in-order issue, out-of-order execute, in-
order retire policy.
The Mic-4 and the OMAP4430 are not really comparable at all because the
OMAP4430 has RISC instructions (i.e., three-register micro-operations) as its ISA
