Hardware Reference
In-Depth Information
Stage
Level 1
inst cache
Fast-loop
look-aside
Fe1
Branch
predictor
Fe2
Instruction issue unit
Instruction
queue
Fe3
Id1
Instruction
decoding
Id2
Re
Instruction renaming
Iss
Instruction issue queue
Ex1
ALU 1
ALU 2
Load-store unit
Level 1
data cache
FPU/
NEON
Ex2
Mult
Level 2
unified
cache
Ex3
WB
Retirement
Figure 4-49. A simplified representation of the OMAP4430's Cortex A9 pipeline.
After completing execution, instructions enter the WB (WriteBack) stage
where each instruction updates the physical register file immediately. Potentially
later, when the instruction is the oldest one in flight, it will write its register result
to the architectural register file. If a trap or interrupt occurs, it is these values, not
those in the physical registers, that are made visible. The act of storing the register
in the architectural file is equivalent to retirement in the Core i7. In addition, in the
WB stage, any store instructions now complete writing their results to the L1 data
cache.
 
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