Hardware Reference
In-Depth Information
To shared L3 cache
Memory subsystem
Execution unit
Level 1
data cache
System interface
Level 2 cache
(instructions and data)
Integer ALUs, floating-point
units, store buffer
Fetch/decode
unit
Micro-op
cache
Renaming,
Scheduling
Retirement
unit
Level 1
inst cache
Branch
predictor
Front end
Out-of-order control
Figure 4-46.
The block diagram of the Core i7's Sandy Bridge microarchitecture.
associative cache with 64-byte cache lines. The shared L3 cache varies in size
from 1 MB to 20 MB. If you pay more cash to Intel you get more cache in return.
Regardless of its size, the L3 is organized as a 12-way associative cache with
64-byte cache lines. In the event that an access to the L3 cache misses, it is sent to
external RAM via the DDR3 RAM bus.
Associated with the L1 cache are two prefetch units (not shown in the figure)
that attempt to prefetch data from lower levels of the memory system into the L1
before they are needed. One prefetch unit prefetches the next memory block when
it detects that a sequential ''stream'' of memory is being fetched into the processor.
A second, more sophisticated, prefetcher tracks the sequence of addresses from
specific program loads and stores. If they progress in a regular stride (e.g.,
0x1000...0x1020...0x1040...) it will prefetch the next element likely to be accessed
in advance of the program. This stride-oriented prefetching does wonders for pro-
grams that are marching through arrays of structured variables.
The memory subsystem in Fig. 4-46 is connected to both the front end and the
L1 data cache. The front end is responsible for fetching instructions from the
memory subsystem, decoding them into RISC-like micro-ops, and storing them
into two instruction storage caches. All instructions fetched are placed into the L1
(level 1) instruction cache. The L1 cache is 32 KB in size, organized as an 8-way
associative cache with 64-byte blocks. As instructions are fetched from the L1
cache, they enter the decoders which determine the sequence of micro-ops used to
