Hardware Reference
In-Depth Information
components in Fig. 4-35. The Mic-4 automatically prefetches a stream of bytes
from memory, decodes them into IJVM instructions, converts them to a sequence
of micro-operations using a ROM, and queues them for use as needed. The first
three stages of the pipeline can be tied to the data path clock if desired, but there
will not always be work to do. For example, the IFU certainly cannot feed a new
IJVM opcode to the decoding unit on every clock cycle because IJVM instructions
take several cycles to execute and the queue would rapidly overflow.
1
2
3
4
5
6
7
Write
back
IFU
Decoder
Queue
Operands
Exec
Memory
Figure 4-36.
The Mic-4 pipeline.
On each clock cycle, the
MIR
s are shifted forward and the micro-operation at
the bottom of the queue is copied into
MIR1
to start its execution. The control sig-
nals from the four
MIR
s then spread out through the data path, causing actions to
occur. Each
MIR
controls a different portion of the data path and thus different
microsteps.
In this design we have a deeply pipelined CPU, which allows the individual
steps to be very short and thus the clock frequency high. Many CPUs are designed
in essentially this way, especially those that have to implement an older (CISC) in-
struction set. For example, the Core i7 implementation is conceptually similar to
the Mic-4 in some ways, as we will see later in this chapter.
All computer manufacturers want their systems to run as fast as possible. In
this section, we will look at a number of advanced techniques currently being
investigated to improve system (primarily CPU and memory) performance. Due to
the highly competitive nature of the computer industry, the lag between new re-
search ideas that can make a computer faster and their incorporation into products
is surprisingly short. Consequently, most of the ideas we will discuss are already
in use in a wide variety of existing products.
The ideas to be discussed fall into roughly two categories: implementation im-
provements and architectural improvements. Implementation improvements are
ways of building a new CPU or memory to make the system run faster without
changing the architecture. Modifying the implementation without changing the ar-
chitecture means that old programs will run on the new machine, a major selling
point. One way to improve the implementation is to use a faster clock, but this is
