Hardware Reference
In-Depth Information
Label
Operations
Comments
ifeq1
MAR = SP = SP
−
1; rd
Read in next-to-top word of stack
ifeq2
OPC = TOS
Save TOS in OPC temporarily
ifeq3
TOS = MDR
Put new top of stack in TOS
ifeq4
Z = OPC; if (Z) goto T; else goto F
Branch on Z bit
if icmpeq1
MAR = SP = SP
−
1; rd
Read in next-to-top word of stack
if icmpeq2
MAR = SP = SP
−
1
Set MAR to read in new top-of-stack
if icmpeq3
H = MDR; rd
Copy second stack word to H
if icmpeq4
OPC = TOS
Save TOS in OPC temporarily
if icmpeq5
TOS = MDR
Put new top of stack in TOS
if icmpeq6
Z = H
−
OPC; if (Z) goto T; else goto F If top 2 words are equal, goto T, else goto F
T
H=PC
−
1; goto goto2
Same as goto1
F
H = MBR2
Touch bytes in MBR2 to discard
F2
goto (MBR1)
invokevirtual1
MAR = CPP + MBR2U; rd
Put address of method pointer in MAR
invokevirtual2
OPC = PC
Save Return PC in OPC
invokevirtual3
PC = MDR
Set PC to 1st byte of method code.
invokevirtual4
TOS = SP
−
MBR2U
TOS = address of OBJREF
−
1
invokevirtual5
TOS = MAR=H=TOS+1
TOS=address of OBJREF
invokevirtual6
MDR = SP + MBR2U + 1; wr
Overwrite OBJREF with link pointer
invokevirtual7
MAR = SP = MDR
Set SP, MAR to location to hold old PC
invokevirtual8
MDR = OPC; wr
Prepare to save old PC
invokevirtual9
MAR = SP = SP + 1
Inc. SP to point to location to hold old LV
invokevirtual10 MDR = LV; wr
Save old LV
invokevirtual11
LV = TOS; goto (MBR1)
Set LV to point to zeroth parameter.
ireturn1
MAR = SP = LV; rd
Reset SP, MAR to read Link ptr
ireturn2
Wait for link ptr
ireturn3
LV = MAR = MDR; rd
Set LV, MAR to link ptr; read old PC
ireturn4
MAR = LV + 1
Set MAR to point to old LV; read old LV
ireturn5
PC = MDR; rd
Restore PC
ireturn6
MAR = SP
ireturn7
LV = MDR
Restore LV
ireturn8
MDR = TOS; wr; goto (MBR1)
Save return value on original top of stack
Figure 4-30.
The microprogram for the Mic-2 (part 2 of 2).
Are we crazy? (
Hint
: No.) The point of inserting the latches is twofold:
1. We can speed up the clock because the maximum delay is now shorter.
2. We can use all parts of the data path during every cycle.
By breaking up the data path into three parts, we reduce the maximum delay
with the result that the clock frequency can be higher. Let us suppose that by
breaking the data path cycle into three time intervals, each one is about 1/3 as long
as the original, so we can triple the clock speed. (This is not totally realistic, since
we have also added two more registers into the data path, but as a first approxima-
tion it will do.)
Because we have been assuming that all memory reads and writes can be satis-
fied out of the level 1 cache, and this cache is made out of the same material as the
