Hardware Reference
In-Depth Information
Address
Control store
0
×
1FF
Microinstruction
execution order
WIDE
ILOAD
ILOAD
wide_iload1
3
0
×
115
0
×
100
Main1
1
1
wide1
2
0
×
C4
iload1
2
0
15
×
0
×
00
Figure 4-20.
The initial microinstruction sequence for
ILOAD
and
WIDE ILOAD
.
The addresses are examples.
interpretation of
WIDE ISTORE
starts at 0x136 (instead of 0x36), and so on. In this
way, every
WIDE
opcode starts at an address 256 (i.e., 0x100) words higher in the
control store higher than the corresponding regular opcode. The initial sequence of
microinstructions for both
ILOAD
and
WIDE ILOAD
is shown in Fig. 4-20.
Once the code is reached for implementing
WIDE ILOAD
(0x115), the code dif-
fers from normal
ILOAD
only in that the index must be constructed by concatenat-
ing 2 index bytes instead of simply sign-extending a single byte. The concatena-
tion and subsequent addition must be accomplished in stages, first copying
INDEX
BYTE 1
into
H
shifted left by 8 bits. Since the index is an unsigned integer,
MBR
is
zero-extended using
MBRU
. Now the second byte of the index is added (the addi-
tion operation is identical to concatenation since the low-order byte of
H
is now
zero, guaranteeing that there will be no carry between the bytes), with the result
again stored in
H
. From here on, the operation can proceed exactly as if it were a
standard
ILOAD
. Rather than duplicate the final instructions of
ILOAD
(
iload3
to
iload5
), we simply branch from
wide iload4
to
iload3
. Note, however, that
PC
must
be incremented twice during the execution of the instruction in order to leave it
pointing to the next opcode. The
ILOAD
instruction increments it once;
the
WIDE ILOAD
sequence also increments it once.
The same situation occurs for
WIDE ISTORE
: after the first four microinstruc-
tions are executed (
wide istore1
to
wide istore4
), the sequence is the same as the