Hardware Reference
In-Depth Information
Z=TOS
runs
TOS
through the ALU, thus setting the
Z
(and
N
) flip-flops, but it does not do a
store into any register. What using
Z
or
N
as a destination really does is tell the
microassembler to set all the bits in the
C
field of Fig. 4-5 to 0. The data path ex-
ecutes a normal cycle, with all normal operations allowed, but no registers are writ-
ten to. Note that it does not matter whether the destination is
N
or
Z
; the micro-
instruction generated by the microassembler is identical. Programmers who inten-
tionally choose the ''wrong'' one should be forced to work on a 4.77-MHz original
IBM PC for a week as punishment.
The syntax for telling the microassembler to set the
JAMZ
bit is
if (Z) goto L1; else goto L2
Since the hardware requires these two addresses to be identical in their low-order 8
bits, it is up to the microassembler to assign them such addresses. On the other
hand, since
L2
can be anywhere in the bottom 256 words of the control store, the
microassembler has a lot of freedom in finding an available pair.
Normally, these two statements will be combined, for example,
Z=TOS
; if (Z) goto L1; else goto L2
The effect of this statement is that MAL generates a microinstruction in which
TOS
is run through the ALU (but not stored anywhere) so that its value sets the
Z
bit.
Shortly after
Z
has been loaded from the ALU condition bit, it is ORed into the
high-order bit of
MPC
, forcing the address of the next microinstruction to be
fetched from either
L2
or
L1
(which must be exactly 256 more than
L2
).
MPC
will
be stable and ready to use for fetching the next microinstruction.
Finally, we need a notation for using the
JMPC
bit. The one we will use is
goto (MBR OR
value
)
This syntax tells the microassembler to use
value
for
NEXT ADDRESS
and set the
JMPC
bit so that
MBR
is ORed into
MPC
along with
NEXT ADDRESS
.If
value
is 0,
which is the normal case, it is sufficient to just write
goto (MBR)
Note that only the low-order 8 bits of
MBR
are wired to
MPC
(see Fig. 4-6), so the
issue of sign extension (i.e.,
MBR
versus
MBRU
) does not arise here. Also note that
the
MBR
available at the end of the current cycle is the one used. A fetch started in
this
microinstruction is too late to affect the choice of the next microinstruction.
We have finally reached the point where we can put all the pieces together.
Figure 4-17 is the microprogram that runs on Mic-1 and interprets IJVM. It is a
surprisingly short program—only 112 microinstructions total. Three columns are
