Hardware Reference
In-Depth Information
instruction that can be reduced by two cycles now runs twice as fast. And this
speedup is obtained every time we execute the instruction.
One possible approach is simply to list the signals that should be activated
each clock cycle. Suppose that in one cycle we want to increment the value of
SP
.
We also want to initiate a read operation, and we want the next instruction to be the
one residing at location 122 in the control store. We might write
ReadRegister = SP, ALU = INC, WSP, Read, NEXT ADDRESS = 122
where
WSP
means ''write the
SP
register.'' This notation is complete but hard to
understand. Instead we will combine the operations in a natural and intuitive way
to capture the effect of what is happening:
SP=SP+1;rd
Let us call our high-level Micro Assembly Language ''
MAL
'' (French for
''sick,'' something you become if you have to write too much code in it).
MAL
is
tailored to reflect the characteristics of the microarchitecture. During each cycle,
any of the registers can be written, but typically only one is. Only one register can
be gated to the B side of the ALU. On the A side, the choices are +1, 0,
1, and
the register
H
. Thus we can use a simple assignment statement, as in Java, to indi-
cate the operation to be performed. For example, to copy something from
SP
to
MDR
, we can say
−
MDR=SP
To indicate the use of the ALU functions other than passing through the B bus,
we can write, for example,
MDR=H+SP
which adds the contents of the
H
register to
SP
and writes the result into
MDR
. The
+ operator is commutative (which means that the order of the operands does not
matter), so the above statement can also be written as
MDR=SP+H
and generate the same 36-bit microinstruction, even though strictly speaking
H
must be the left ALU operand.
We have to be careful to use only permitted operations. The most important of
them are shown in Fig. 4-16, where
SOURCE
can be any of
MDR
,
PC
,
MBR
,
MBRU
,
SP
,
LV
,
CPP
,
TOS
,or
OPC
(
MBRU
implies the unsigned version of
MBR
). These reg-
isters can all act as sources to the ALU on the B bus. Similarly,
DEST
can be any
of
MAR
,
MDR
,
PC
,
SP
,
LV
,
CPP
,
TOS
,
OPC
,or
H
, all of which are possible destina-
tions for the ALU output on the C bus. This format is deceptive because many
seemingly reasonable statements are illegal. For example,
MDR=SP+MDR
