Hardware Reference
In-Depth Information
Address
Addr
JAM
Data path control bits
0x75
0x92
001
JAMZ bit set
One of
these
will follow
0x75
depending
on Z
0x92
0x192
Figure 4-7. A microinstruction with JAMZ set to 1 has two potential successors.
any of 256 addresses can be specified, determined solely by the bits present in
MBR . In a typical use, MBR contains an opcode, so the use of JMPC will result in a
unique selection for the next microinstruction to be executed for every possible op-
code. This method is useful for quickly branching directly to the function corres-
ponding to the just-fetched opcode.
Understanding the timing of the machine is critical to what will follow, so it is
perhaps worth repeating. We will do it in terms of subcycles, since this is easy to
visualize, but the only real clock events are the falling edge, which starts the cycle,
and the rising edge, which loads the registers and the N and Z flip-flops. Please
refer to Fig. 4-3 once more.
During subcycle 1, initiated by the falling edge of the clock, MIR is loaded
from the address currently held in MPC . During subcycle 2, the signals from MIR
propagate out and the B bus is loaded from the selected register. During subcycle
3, the ALU and shifter operate and produce a stable result. During subcycle 4, the
C bus, memory buses, and ALU values become stable. At the rising edge of the
clock, the registers are loaded from the C bus, N and Z flip-flops are loaded, and
MBR and MDR get their results from the memory operation started at the end of the
previous data path cycle (if any). As soon as MBR is available, MPC is loaded in
preparation for the next microinstruction. Thus MPC gets its value sometime dur-
ing the middle of the interval when the clock is high but after MBR / MDR are ready.
It could be either level triggered (rather than edge triggered), or edge trigger a
fixed delay after the rising edge of the clock. All that matters is that MPC is not
loaded until the registers it depends on ( MBR , N , and Z ) are ready. As soon as the
clock falls, MPC can address the control store and a new cycle can begin.
Note that each cycle is self contained. It specifies what goes onto the B bus,
what the ALU and shifter are to do, where the C bus is to be stored, and finally,
what the next MPC value should be.
One final note about Fig. 4-6 is worth making. We have been treating MPC as
a proper register, with 9 bits of storage capacity that is loaded while the clock is
high. In reality, there is no need to have a register there at all. All of its inputs can
be fed directly through, right to the control store. As long as they are present at the
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