Hardware Reference
In-Depth Information
next microinstruction begins after
MIR
has been loaded and is stable. First, the
NEXT ADDRESS
field is copied to
MPC
. While this copy is taking place, the
JAM
field is inspected. If it has the value 000, nothing else is done; when the copy of
NEXT ADDRESS
completes,
MPC
will point to the next microinstruction.
If one or more of the
JAM
bits are 1, more work is needed. If
JAMN
is set, the
1-bit
N
flip-flop is ORed into the high-order bit of
MPC
. Similarly, if
JAMZ
is set,
the 1-bit
Z
flip-flop is ORed there. If both are set, both are ORed there. The rea-
son that the
N
and
Z
flip-flops are needed is that after the rising edge of the clock
(while the clock is high), the B bus is no longer being driven, so the ALU outputs
can no longer be assumed to be correct. Saving the ALU status flags in
N
and
Z
makes the correct values available and stable for the
MPC
computation, no matter
what is going on around the ALU.
In Fig. 4-6, the logic that does this computation is labeled ''High bit.'' The
Boolean function it computes is
F
=(
JAMZ AND Z
)
OR
(
JAMN AND N
)
OR NEXT ADDRESS
[8]
Note that in all cases,
MPC
can take on only one of two possible values:
1. The value of
NEXT ADDRESS
.
2. The value of
NEXT ADDRESS
with the high-order bit ORed with 1.
No other possibilities make sense. If the high-order bit of
NEXT ADDRESS
was al-
ready 1, using
JAMN
or
JAMZ
makes no sense.
Note that when the
JAM
bits are all zeros, the address of the next microinstruc-
tion to be executed is simply the 9-bit number in the
NEXT ADDRESS
field. When
either
JAMN
or
JAMZ
is 1, there are two potential successors:
NEXT ADDRESS
and
NEXT ADDRESS
ORed with 0x100 (assuming that
NEXT ADDRESS
0xFF). (Note
that 0x indicates that the number following it is in hexadecimal.) This point is il-
lustrated in Fig. 4-7. The current microinstruction, at location 0x75, has
NEXT AD-
DRESS
= 0x92 and
JAMZ
set to 1. Consequently, the next address of the microin-
struction depends on the
Z
bit stored on the previous ALU operation. If the
Z
bit is
0, the next microinstruction comes from 0x92. If the
Z
bit is 1, the next microin-
struction comes from 0x192.
The third bit in the
JAM
field is
JMPC
. If it is set, the 8
MBR
bits are bitwise
ORed with the 8 low-order bits of the
NEXT ADDRESS
field coming from the cur-
rent microinstruction. The result is sent to
MPC
. The box with the label ''O'' in
Fig. 4-6 does an OR of
MBR
with
NEXT ADDRESS
if
JMPC
is 1 but just passes
NEXT ADDRESS
through to
MPC
if
JMPC
is 0. When
JMPC
is 1, the low-order 8
bits of
NEXT ADDRESS
are normally zero. The high-order bit can be 0 or 1, so the
NEXT ADDRESS
value used with
JMPC
is normally 0x000 or 0x100. The reason
for sometimes using 0x000 and sometimes using 0x100 will be discussed later.
The ability to OR
MBR
together with
NEXT ADDRESS
and store the result in
MPC
allows an efficient implementation of a multiway branch (jump). Notice that
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