THE MICROARCHITECTURE LEVEL - Structured Computer Organization - page 251

4.1.2 Microinstructions
To control the data path of Fig. 4-1, we need 29 signals. These can be divided
into five functional groups, as described below.
9 Signals to control writing data from the C bus into registers.
9 Signals to control enabling registers onto the B bus for ALU input.
8 Signals to control the ALU and shifter functions.
2 Signals (not shown) to indicate memory read/write via MAR / MDR .
1 Signal (not shown) to indicate memory fetch via PC / MBR .
The values of these 29 control signals specify the operations for one cycle of the
data path. A cycle consists of gating values out of registers and onto the B bus,
propagating the signals through the ALU and shifter, driving them onto the C bus,
and finally writing the results in the appropriate register or registers. In addition, if
a memory read data signal is asserted, the memory operation is started at the end of
the data path cycle, after MAR has been loaded. The memory data are available at
the very end of the following cycle in MBR or MDR and can be used in the cycle
after that . In other words, a memory read on either port initiated at the end of
cycle k delivers data that cannot be used in cycle k + 1, but only in cycle k +2or
later.
This seemingly counterintuitive behavior is explained by Fig. 4-3. The memo-
ry control signals are not generated in clock cycle 1 until just after MAR and PC are
loaded at the rising edge of the clock, toward the end of clock cycle 1. We will as-
sume the memory puts its results on the memory buses within one cycle so that
MBR and/or MDR can be loaded on the next rising clock edge, along with the other
registers.
Put in other words, we load MAR at the end of a data path cycle and start the
memory shortly thereafter. Consequently, we cannot really expect the results of a
read operation to be in MDR at the start of the next cycle, especially if the clock
pulse is narrow. There is just not enough time if the memory takes one clock cycle.
One data path cycle must intervene between starting a memory read and using the
result. Of course, other operations can be performed during that cycle, just not
those that need the memory word.
The assumption that the memory takes one cycle to operate is equivalent to as-
suming that the level 1 cache hit rate is 100%. This assumption is never true, but
the complexity introduced by a variable-length memory cycle time is more than we
want to deal with here.
Since MBR and MDR are loaded on the rising edge of the clock, along with all
the other registers, they may be read during cycles when a new memory read is
being performed. They return the old values, since the read has not yet had time to
overwrite them. There is no ambiguity here; until new values are loaded into MBR