Hardware Reference
In-Depth Information
their contents onto the B bus. The output of the ALU drives the shifter and then
the C bus, whose value can be written into one or more registers at the same time.
There is no A bus for the moment; we will add one later.
The ALU is identical to the one shown in Figs. 3-18 and 3-19. Its function is
determined by six control lines. The short diagonal line labeled ''6'' in Fig. 4-1 in-
dicates that there are six ALU control lines. These are
F
0
and
F
1
for determining
the ALU operation,
ENA
and
ENB
for individually enabling the inputs,
INVA
for
inverting the left input, and
INC
for forcing a carry into the low-order bit, ef-
fectively adding 1 to the result. However, not all 64 combinations of ALU control
lines do something useful.
Some of the more interesting combinations are shown in Fig. 4-2. Not all of
these functions are needed for IJVM, but for the full JVM many of them would
come in handy. In many cases, there are multiple possibilities for achieving the
same result. In this table, + means arithmetic plus and
−
means arithmetic minus,
so, for example,
−
A
means the two's complement of
A
.
F
0
F
1
ENA ENB INVA INC Function
011 0 0 0A
010 1 0 0
B
011 0 1 0
A
101 1 0 0B
1 1 1 1 0 0 A+B
1 1 1 1 0 1 A+B+1
1 1 1 0 0 1 A+1
1 1 0 1 0 1 B+1
111 1 1 1B
−
A
110 1 1 0B
−
1
111 0 1 1
−
A
0 0 1 1 0 0 A AND B
0 1 1 1 0 0 AORB
010 0 0 00
110 0 0 11
110 0 1 0
−
1
Figure 4-2.
Useful combinations of ALU signals and the function performed.
The ALU of Fig. 4-1 needs two data inputs: a left input (A) and a right input
(B). Attached to the left input is a holding register,
H
. Attached to the right input
is the B bus, which can be loaded from any one of nine sources, indicated by the
nine gray arrows touching it. An alternative design, with two full buses, has a dif-
ferent set of trade-offs and will be discussed later in this chapter.
