Hardware Reference
In-Depth Information
27.
In Fig. 3-38(b),
T
ML
is specified to be at least 2 nsec.
Can
you envision a chip in
which it is negative? Specifically, could the CPU assert
MREQ
before the address was
stable? Why or why not?
28.
Assume that the block transfer of Fig. 3-42 were done on the bus of Fig. 3-38. How
much more bandwidth is obtained by using a block transfer over individual transfers
for long blocks? Now assume that the bus is 32 bits wide instead of 8 bits wide.
Answer the question again.
29.
Denote the transitio
n time
s of the address lines of Fig. 3-39 as
T
A1
and
T
A2
, and the
transition times of
MREQ
as
T
MREQ
1
and
T
MREQ
2
, and so on. Write down all the
inequalities implied by the full handshake.
30.
Multicore chips, with multiple CPUs on the same die, are becoming popular. What ad-
vantages do they have over a system consisting of multiple PCs connected by Ether-
net?
31.
Why have multicore chips suddenly appeared? Are there technological factors that
have paved the way? Does Moore's law play a role here?
32.
What is the difference between the memory bus and the PCI bus?
33.
Most 32-bit buses permit 16-bit reads and writes. Is there any ambiguity about where
to place the data? Discuss.
34.
Many CPUs have a special bus cycle type for interrupt acknowledge. Why?
35.
A 64-bit computer with a 400-MHz bus requires four cycles to read a 64-bit word.
How much bus bandwidth does the CPU consume in the worst case, that is, assuming
back-to-back reads or writes all the time?
36.
A 64-bit computer with a 400-MHz bus requires four cycles to read a 64-bit word.
How much bus bandwidth does the CPU consume in the worst case, that is, assuming
back-to-back reads or writes all the time?
37.
A 32-bit CPU with address lines A2-A31 requires all memory references to be
aligned. That is, words have to be addressed at multiples of 4 bytes, and half-words
have to be addressed at even bytes. Bytes can be anywhere. How many legal combi-
nations are there for memory reads, and how many pins are needed to express them?
Give two answers and make a case for each one.
38.
Modern CPU chips have one, two, or even three levels of cache on chip. Why are mul-
tiple levels of cache needed?
39.
Suppose that a CPU has a level 1 cache and a level 2 cache, with access times of 1 nsec
and 2 nsec, respectively. The main memory access time is 10 nsec. If 20% of the ac-
cesses are level 1 cache hits and 60% are level 2 cache hits, what is the average access
time?
40.
Calculate the bus bandwidth needed to display 1280
960) color video at 30
frames/sec. Assume that the data must pass over the bus twice, once from the CD-
ROM to the memory and once from the memory to the screen.
41.
Which of the signals of Fig. 3-55 is not strictly necessary for the bus protocol to work?
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