Hardware Reference
In-Depth Information
carry to ripple through to the high-order stage may be unacceptably long. Design an
adder that works faster. Hint : Each C i can be expressed in terms of the operand bits
A i − 1 and B i − 1 as well as the carry C i − 1 . Using this relation it is possible to express C i
as a function of the inputs to stages 0 to i
1, so all the carries can be generated simul-
taneously.
15. If all the gates in Fig. 3-18 have a propagation delay of 1 nsec, and all other delays can
be ignored, what is the earliest time a circuit using this design can be sure of having a
valid output bit?
16. The ALU of Fig. 3-19 is capable of doing 8-bit 2's complement additions. Is it also ca-
pable of doing 2's complement subtractions? If so, explain how. If not, modify it to be
able to do subtractions.
17. A 16-bit ALU is built up of 16 1-bit ALUs, each one having an add time of 10 nsec. If
there is an additional 1-nsec delay for propagation from one ALU to the next, how long
does it take for the result of a 16-bit add to appear?
18. Sometimes it is useful for an 8-bit ALU such as Fig. 3-19 to generate the constant
1
as output. Give two different ways this can be done. For each way, specify the values
of the six control signals.
19. What is the quiescent state of the S and R inputs to an SR latch built of two NAND
gates?
20. The circuit of Fig. 3-25 is a flip-flop that is triggered on the rising edge of the clock.
Modify this circuit to produce a flip-flop that is triggered on the falling edge of the
clock.
21. The 4
3 memory of Fig. 3-28 uses 22 AND gates and three OR gates. If the circuit
were to be expanded to 256
×
8, how many of each would be needed?
22. To help meet the payments on your new personal computer, you have taken up consult-
ing for fledgling SSI chip manufacturers. One of your clients is thin ki ng about putting
out a chip containing four D flip-flops, each containing both Q and Q , on request of a
potentially important customer. The proposed design has all four clock signals ganged
together, also on request. Neither preset nor clear is present. Your assignment is to
give a professional evaluation of the design.
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23. As more and more memory is squeezed onto a single chip, the number of pins needed
to address it also increases. It is often inconvenient to have large numbers of address
pins on a chip. Devise a way to address 2 n words of memory using fewer than n pins.
24. A computer with a 32-bit wide data bus uses 1M
1 dynamic RAM memory chips.
What is the smallest memory (in bytes) that this computer can have?
25. Referring to the timing diagram of Fig. 3-38, suppose that you slowed the clock down
to a period of 20 nsec instead of 10 nsec as shown but the timing constraints remained
unchanged. How much time would the memory have to get the data onto the bus dur-
ing T 3 after MREQ was asserted, in the worst case?
26. Again referring to Fig. 3-38, suppose that the clock remained at 100 MHz, but T DS was
increased to 4 nsec. Could 10-nsec memory chips be used?
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