Hardware Reference
In-Depth Information
A
0
Address bus
A
15
CS
CS
CS
2K × 8
EPROM
2K × 8
RAM
PI0
(a)
A
0
Address bus
A
15
CS
CS
CS
2K × 8
EPROM
2K × 8
RAM
PI0
(b)
Figure 3-61.
(a) Full address decoding. (b) Partial address decoding.
