Hardware Reference
In-Depth Information
over the PCI bus system, which does not have any provision for verification and re-
transmission of data sent over the bus.
To prevent having a fast sender bury a slow receiver in packets it cannot han-
dle, a flow control mechanism is used. The mechanism is that the receiver gives
the transmitter a certain number of credits, basically corresponding to the amount
of buffer space it has available to store incoming packets. When the credits are
used up, the transmitter has to stop sending until it is given more credits. This
scheme, which is widely used in all networks, prevents losing data due to a mis-
match of transmitter and receiver speeds.
The transaction layer handles bus actions. Reading a word from memory re-
quires two transactions: one initiated by the CPU or DMA channel requesting
some data and one initiated by the target supplying the data. But the transaction
layer does more than handle pure reads and writes. It adds value to the raw packet
transmission offered by the link layer. To start with, it can divide each lane into up
to eight virtual circuits , each handling a different class of traffic. The transaction
layer can tag packets according to their traffic class, which may include attributes
such as high priority, low priority, do not snoop, may be delivered out of order, and
more. The switch may use these tags when deciding which packet to handle next.
Each transaction uses one of four address spaces:
1. Memory space (for ordinary reads and writes).
2. I/O space (for addressing device registers).
3. Configuration space (for system initialization, etc.).
4. Message space (for signaling, interrupts, etc.).
The memory and I/O spaces are similar to what current systems have. The config-
uration space can be used to implement features such as plug-and-play. The mes-
sage space takes over the role of many of the existing control signals. Something
like this space is needed because none of the PCI bus' control lines exist in PCI
Express.
The software layer interfaces the PCI Express system to the operating system.
It can emulate the PCI bus, making it possible to run existing operating systems
unmodified on PCI Express systems. Of course, operating like this will not exploit
the full power of PCI Express, but backward compatibility is a necessary evil that
is needed until operating systems have been modified to fully utilize PCI Express.
Experience shows this can take a while.
The flow of information is illustrated in Fig. 3-57(b). When a command is
given to the software layer, it hands it to the transaction layer, which formulates it
in terms of a header and a payload. These two parts are then passed to the link
layer, which attaches a sequence number to the front and a CRC to the back. This
enlarged packet is then passed on to the physical layer, which adds framing infor-
mation on each end to form the physical packet that is actually transmitted. At the
 
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