Hardware Reference
In-Depth Information
Bus cycle
Read
Idle
Write
T
1
T
2
T
3
T
4
T
5
T
6
T
7
Φ
Turnaround
AD
Address
Data
Address
Data
C/BE#
Read cmd
Enable
Write cmd
Enable
FRAME#
IRDY#
DEVSEL#
TRDY#
Figure 3-55.
Examples of 32-bit PCI bus transactions. The first three cycles are
used for a read operation, then an idle cycle, and then three cycles for a write op-
eration.
Although the PCI bus works adequately for most current applications, the need
for greater I/O bandwidth is making a mess of the once-clean internal PC architec-
ture. In Fig. 3-52, it is clear that the PCI bus is no longer the central element that
holds the parts of the PC together. The bridge chip has taken over part of that role.
The essence of the problem is that increasingly many I/O devices are too fast
for the PCI bus. Cranking up the clock frequency on the bus is not a good solution
because then problems with bus skew, crosstalk between the wires, and capacitance
effects just get worse. Every time an I/O device gets too fast for the PCI bus (like
the graphics card, hard disk, network, etc.), Intel adds a new special port to the
bridge chip to allow that device to bypass the PCI bus. Clearly, this is not a long-
term solution either.
Another problem with the PCI bus is that the cards are quite large. Standard
PCI cards are generally 17.5 cm by 10.7 cm and low-profile cards are 12.0 cm by
3.6 cm. Neither of these fit well in laptop computers and and certainly not in
mobile devices. Manufacturers would like to produce even smaller devices. Also,
