Hardware Reference
In-Depth Information
down, the address and data lines are multiplexed. In this way, only 64 pins are
needed on PCI cards for address plus data signals, even though PCI supports 64-bit
addresses and 64-bit data.
The multiplexed address and data pins work as follows. On a read operation,
during cycle 1, the master puts the address onto the bus. On cycle 2, the master re-
moves the address and the bus is turned around so the slave can use it. On cycle 3,
the slave outputs the data requested. On write operations, the bus does not have to
be turned around because the master puts on both the address and the data. Never-
theless, the minimum transaction is still three cycles. If the slave is not able to re-
spond in three cycles, it can insert wait states. Block transfers of unlimited size are
also allowed, as well as several other kinds of bus cycles.
PCI Bus Arbitration
To use the PCI bus, a device must first acquire it. PCI bus arbitration uses a
centralized bus arbiter, as shown in Fig. 3-53. In most designs, the bus arbiter is
built into one of the bridge chips. Every PCI device has two dedicated lines run-
ning from it to the arbiter. One line,
REQ#
, is used to request the bus. The other
line,
GNT#
, is used to receive bus grants. Note:
REQ#
is PCI-speak for
REQ
.
PCI
arbiter
PCI
device
PCI
device
PCI
device
PCI
device
Figure 3-53.
The PCI bus uses a centralized bus arbiter.
To request the bus, a PCI device (including the CPU) asserts
REQ#
and waits
until it sees its
GNT#
line asserted by the arbiter. When that event happens, the de-
vice can use the bus on the next cycle. The algorithm used by the arbiter is not de-
fined by the PCI specification. Round-robin arbitration, priority arbitration, and
other schemes are all allowed. Clearly, a good arbiter will be fair, so as not to let
some devices wait forever.
A bus grant is for only one transaction, although the length of this transaction
is theoretically unbounded. If a device wants to run a second transaction and no
other device is requesting the bus, it can go again, although often one idle cycle be-
tween transactions has to be inserted. However, under special circumstances, in
