Hardware Reference
In-Depth Information
Watchdog
timer
debugWIRE
Power
supervision
POR/BOD &
RESET
Watchdog
oscillator
Program
logic
Oscillator
circuits/
clock
generation
Flash
SRAM
CPU
EEPROM
AVCC
AREF
GND
2
8bit T/C 0
16bit T/C 1
A/D conv.
Analog
comp.
Internal
bandgap
6
8bit T/C 2
USART 0
SPI
TWI
PORT D (8)
PORT B (8)
PORT C (7)
RESET
XTAL[1..2]
PD[0..7]
PB[0..7]
PC[0..6]
ADC[6..7]
Figure 3-50. The internal architecture and logical pinout of the ATmega168.
 
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