Hardware Reference
In-Depth Information
You might be wondering how the Core i7 knows when to expect its READ
command data to return, and when it can make a new memory request. The answer
is that it knows when to receive and initiate requests because it fully models the in-
ternal activities of each attached DDR3 DRAM. Thus, it will anticipate the return
of data in the correct cycle, and it will know to avoid initiating a precharge opera-
tion until two cycles after its last read operation. The Core i7 can anticipate all of
these activities because the DDR3 memory interface is a
synchronous memory
interface
. Thus, all activities take a well-known number of DDR3 bus cycles.
Even with all of this knowledge, building a high-performance fully pipelined
DDR3 memory interface is a nontrivial task, requiring many internal timers and
conflict detectors to implement efficient DRAM request handling.
As our second example of a CPU chip, we will now examine the Texas Instru-
ments (TI) OMAP4430
system-on-a-chip
(
SoC
). The OMAP4430 implements
the ARM instruction set, and it is targeted at mobile and embedded applications
such as smartphones, tablets, and Internet appliances. Aptly named, a sys-
tem-on-a-chip incorporates a wide range of devices such that the SoC combined
with physical peripherals (touchscreen, flash memory, etc.) implements a complete
computing device.
The OMAP4430 SoC includes two ARM A9 cores, additional accelerators,
and a wide range of peripheral interfaces. The internal organization of the
OMAP4430 is shown in Fig. 3-47. The ARM A9 cores are 2-wide superscalar
microarchitectures. In addition, there are three more accelerator processors on the
OMAP4430 die: a POWERVR SGX540 graphics processor, an image signal proc-
essor (ISP), and an IVA3 video processor. The SGX540 provides efficient pro-
grammable 3D rendering, similar to the GPUs found in desktop PCs, albeit smaller
and slower. The ISP is a programmable processor designed for efficient image
manipulation, for the type of operations that would be required in a high-end digi-
tal camera. The IVA3 implements efficient video encoding and decoding, with
enough performance to support 3D applications like those found in handheld game
consoles. Also included in the OMAP4430 SoC is a wide range of peripheral inter-
faces, including a touchscreen and keypad controllers, DRAM and flash interfaces,
USB, and HDMI. Texas Instruments has detailed the roadmap for the OMAP series
of CPUs. Future designs will have more of everything—more ARM cores, more
GPUs, and more diverse peripherals.
The OMAP4430 SoC was introduced in early 2011 with two ARM A9 cores
running at 1 GHz using a 45-nanometer silicon implementation. A key aspect of
the OMAP4430 design is that it performs significant amounts of computation with
very little power, since it is targeted to mobile applications that are powered by a
battery. In battery-powered mobile applications, the more efficiently the design op-
erates, the longer the user can go between battery charges.