Hardware Reference
In-Depth Information
Normally, one word at a time is transferred. However, when caching is used, it
is desirable to fetch an entire cache line (e.g., 8 consecutive 64-bit words) at once.
Often block transfers can be made more efficient than successive individual trans-
fers. When a block read is started, the bus master tells the slave how many words
are to be transferred, for example, by putting the word count on the data lines dur-
ing T 1 . Instead of just returning one word, the slave outputs one word during each
cycle until the count has been exhausted. Figure 3 -42 shows a modified version of
Fig. 3-38(a), but now with an extra signal BLOCK that is asserted to indicate that a
block transfer is requested. In this example, a block read of 4 words takes 6 cycles
instead of 12.
T 1
T 2
T 3
T 4
T 5
T 6
T 7
Φ
ADDRESS
Memory address to be read
DATA
Count
Data
Data
Data
Data
MREQ
RD
WAIT
BLOCK
Figure 3-42. A block transfer.
Other kinds of bus cycles also exist. For example, on a multiprocessor system
with two or more CPUs on the same bus, it is often necessary to make sure that
only one CPU at a time uses some critical data structure in memory. A typical way
to arrange this is to have a variable in memory that is 0 when no CPU is using the
data structure and 1 when it is in use. If a CPU wants to gain access to the data
structure, it must read the variable, and if it is 0, set it to 1. The trouble is, with
some bad luck, two CPUs might read it on consecutive bus cycles. If each one sees
that the variable is 0, then each one sets it to 1 and thinks that it is the only CPU
using the data structure. This sequence of events leads to chaos.
To prevent this situation, multiprocessor systems often have a special
read-modify-write bus cycle that allows any CPU to read a word from memory,
inspect and modify it, and write it back to memory, all without releasing the bus.
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