Hardware Reference
In-Depth Information
The timing speci
ficatio
n further guarantees that the address will be set
up at
least 2 nsec prior to
MREQ
being asserted. This time can be important if
MREQ
drives chip select on the memory chip because some memories require an address
setup time prior to chip select. Clearly, the system designer should not choose a
memory chip that needs a 3-nsec setup time.
The constraints on
T
M
and
T
RL
mean that
MREQ
and
RD
will both be asserted
within 3 nsec from the
T
1
falling clock. In the worst case
, the
mem
ory
chip will
have only 10 + 10
2 = 15 nsec after the assertion of
MREQ
and
RD
to get its
data onto the bus. This constraint is in addition to (and independent of) the
15-nsec interval needed after the address
is stab
le.
T
MH
and
T
RH
tell how long it takes
MREQ
and
RD
to be negated after the data
have been strob
ed
in. Finally,
T
DH
tells how long the memory must hold the data
on the bus after
RD
has been negated. As far as our exam
ple
CPU is concerned, the
memory can remove the data from the bus as soon as
RD
has been negated. On
some actual CPUs, however, the data must be kept stable a little longer.
We would like to point out that Fig. 3-38 is a highly simplified version of real
timing constraints. In reality, many more critical times are always specified.
Nevertheless, it gives a good flavor for how a synchronous bus works.
A last point worth making is that control signals can be asserted high or low. It
is up to the bus designers to determine which is more convenient, but the choice is
essentially arbitrary. One can regard it as the hardware equivalent of a pro-
grammer's choice to represent free disk blocks in a bit map as 0s vs. 1s.
−
3
−
Asynchronous Buses
Although synchronous buses are easy to work with due to their discrete time
intervals, they also have some problems. For example, everything works in multi-
ples of the bus clock. If a CPU and memory are able to complete a transfer in 3.1
cycles, they have to stretch it to 4.0 because fractional cycles are forbidden.
Worse yet, once a bus cycle has been chosen, and memory and I/O cards have
been built for it, it is difficult to take advantage of future improvements in technol-
ogy. For example, suppose a few years after the system of Fig. 3-38 was built, new
memories became available with access times of 8 nsec instead of 15 nsec. These
would get rid of the wait state, speeding up the machine. Then suppose 4-nsec
memories became available. There would be no further gain in performance be-
cause the minimum time for a read is two cycles with this design.
Putting this in slightly different terms, if a synchronous bus has a heteroge-
neous collection of devices, some fast and some slow, the bus has to be geared to
the slowest one and the fast ones cannot use their full potential.
Mixed technology can be handled by going to an asynchronous bus, that is,
one with no master clock, as shown in Fig. 3-39. Inst
ead of
t
yin
g everything to the
clock, when the bus master has asserted the address,
MREQ
,
RD
, and anything else
