Hardware Reference
In-Depth Information
original 20, for reasons of backward compatibility), as illustrated in Fig. 3-37(b).
Unfortunately, more control lines had to be added to deal with the new address
lines. When the 80386 came out, another eight address lines were added, along
with still more control lines, as shown in Fig. 3-37(c). The resulting design (the
EISA bus) is much messier than it would have been had the bus been given 32 lines
at the start.
Not only does the number of address lines tend to grow over time, but so does
the number of data lines, albeit for a different reason. There are two ways to in-
crease the bandwidth of a bus: decrease the bus cycle time (more transfers/sec) or
increase the data bus width (more bits/transfer). Speeding the bus up is possible
(but difficult) because the signals on different lines travel at slightly different
speeds, a problem known as
bus skew
. The faster the bus, the more the skew.
Another problem with speeding up the bus is it will not be backward compati-
ble. Old boards designed for the slower bus will not work with the new one. Inval-
idating old boards makes both the owners and manufacturers of the old boards
unhappy. Therefore the usual approach to improving performance is to add more
data lines, analogous to Fig. 3-37. As you might expect, however, this incremental
growth does not lead to a clean design in the end. The IBM PC and its successors,
for example, went from 8 data lines to 16 and then 32 on essentially the same bus.
To get around the problem of very wide buses, sometimes designers opt for a
multiplexed bus
. In this design, instead of the address and data lines being sepa-
rate, there are, say, 32 lines for address and data together. At the start of a bus op-
eration, the lines are used for the address. Later on, they are used for data. For a
write to memory, for example, this means that the address lines must be set up and
propagated to the memory before the data can be put on the bus. With separate
lines, the address and data can be put on together. Multiplexing the lines reduces
bus width (and cost) but results in a slower system. Bus designers have to careful-
ly weigh all these options when making choices.
Buses can be divided into two distinct categories depending on their clocking.
A
synchronous bus
has a line driven by a crystal oscillator. The signal on this line
consists of a square wave with a frequency generally between 5 and 133 MHz. All
bus activities take an integral number of these cycles, called
bus cycles
. The other
kind of bus, the
asynchronous bus
, does not have a master clock. Bus cycles can
be of any length required and need not be the same between all pairs of devices.
Below we will examine each bus type.
Synchronous Buses
As an example of how a synchronous bus works, consider the timing of
Fig. 3-38(a). In this example, we will use a 100-MHz clock, which gives a bus
cycle of 10 nsec. While this may seem a bit slow compared to CPU speeds of 3