Hardware Reference
In-Depth Information
Universal Serial Bus (modern PCs), and FireWire (consumer electronics). The
world would probably be a better place if all but one would suddenly vanish from
the face of the earth (well, all right, how about all but two?). Unfortunately, stan-
dardization in this area seems very unlikely, as there is already too much invested
in all these incompatible systems.
As an aside, there is another interconnect, PCI Express, that is widely referred
to as a bus but is not a bus at all. We will study it later in this chapter.
Let us now begin our study of how buses work. Some devices that attach to a
bus are active and can initiate bus transfers, whereas others are passive and wait for
requests. The active ones are called
masters
; the passive ones are called
slaves
.
When the CPU orders a disk controller to read or write a block, the CPU is acting
as a master and the disk controller is acting as a slave. However, later on, the disk
controller may act as a master when it commands the memory to accept the words
it is reading from the disk drive. Several typical combinations of master and slave
are listed in Fig. 3-36. Under no circumstances can memory ever be a master.
Master
Slave
Example
CPU
Memory
Fetching instructions and data
CPU
I/O device
Initiating data transfer
CPU
Coprocessor
CPU handing instruction off to coprocessor
I/O device
Memory
DMA (Direct Memory Access)
Coprocessor
CPU
Coprocessor fetching operands from CPU
Figure 3-36.
Examples of bus masters and slaves.
The binary signals that computer devices output are frequently too weak to
power a bus, especially if it is relatively long or has many devices on it. For this
reason, most bus masters are connected to the bus by circuitry called a
bus driver
,
which is essentially a digital amplifier. Similarly, most slaves are connected to the
busbya
bus receiver
. For devices that can act as both master and slave, a combin-
ed circuit called a
bus transceiver
is used. These bus interfaces are often tri-state
devices, to allow them to float (disconnect) when they are not needed, or are
hooked up in a somewhat different way, called
open collector
, that achieves a sim-
ilar effect. When two or more devices on an open-collector line assert the line at
the same time, the result is the Boolean OR of all the signals. This arrangement is
often called
wired-OR
. On most buses, some of the lines are tri-state and others,
which need the wired-OR property, are open collector.
Like a CPU, a bus also has address, data, and control lines. However, there is
not necessarily a one-to-one mapping between the CPU pins and the bus signals.
For example, some CPUs have three pins that encode whether the CPU is doing a
memory read, memory write, I/O read, I/O write, or some other operation. A typi-
cal bus might have one line for memory read, a second for memory write, a third
for I/O read, a fourth for I/O write, and so on. A decoder circuit would then be
