Hardware Reference
In-Depth Information
more control lines to inform the memory that it wants to read (for example) a
word. The memory replies by putting the requested word on the CPU's data pins
and asserting a signal saying that it is done. When the CPU sees this signal, it ac-
cepts the word and carries out the instruction.
The instruction may require reading or writing data words, in which case the
whole process is repeated for each additional word. We will go into the detail of
how reading and writing works below. For the time being, the important thing to
understand is that the CPU communicates with the memory and I/O devices by
presenting signals on its pins and accepting signals on its pins. No other communi-
cation is possible.
Two of the key parameters that determine the performance of a CPU are the
number of address pins and the number of data pins. A chip with
m
address pins
can address up to 2
m
memory locations. Common values of
m
are 16, 32, and 64.
Similarly, a chip with
n
data pins can read or write an
n
-bit word in a single opera-
tion. Common values of
n
are 8, 32, and 64. A CPU with 8 data pins will take
four operations to read a 32-bit word, whereas one with 32 data pins can do the
same job in one operation. Thus, the chip with 32 data pins is much faster but is
invariably more expensive as well.
In addition to address and data pins, each CPU has some control pins. They
regulate the flow and timing of data to and from the CPU and have other miscella-
neous uses. All CPUs have pins for power (usually +1.2 to +1.5 volts), ground,
and a clock signal (a square wave at some well-defined frequency), but the other
pins vary greatly from chip to chip. Nevertheless, the control pins can be roughly
grouped into the following major categories:
1. Bus control.
2. Interrupts.
3. Bus arbitration.
4. Coprocessor signaling.
5. Status.
6. Miscellaneous.
We will briefly describe each of these categories below. When we look at the Intel
Core i7, TI OMAP4430, and Atmel ATmega168 chips later, we will provide more
detail. A generic CPU chip using these signal groups is shown in Fig. 3-34.
The bus control pins are mostly outputs from the CPU to the bus (thus inputs
to the memory and I/O chips) telling whether the CPU wants to read or write mem-
ory or do something else. The CPU uses these pins to control the rest of the sys-
tem and tell it what it wants to do.
The interrupt pins are inputs from I/O devices to the CPU. In most systems,
the CPU can tell an I/O device to start an operation and then go off and do some
