Hardware Reference
In-Depth Information
A LUT, shown in Fig. 3-33(a), is a small programmable memory that produces
a signal output optionally to a register, which is then output to the programmable
interconnect. The programmable memory is used to create an arbitrary logic func-
tion. The LUT in the figure has a 16
4 memory, which can emulate any logic cir-
cuit with 4 bits of input and 4 bits of output. Programming the LUT requires load-
ing the memory with the appropriate responses of the combinational logic being
emulated. In other words, if the combinational logic produces the value
Y
when
given the input
X
, the value
Y
would be written into the LUT at index
X
.
The example design in Fig. 3-32(b) shows how a single 4-input LUT could im-
plement a 3-bit counter with reset. The example counter continually counts up by
adding one (modulo 4) to the current value of the counter, unless the reset signal
CLR
is asserted, in which case the counter resets its value to zero.
To implement the example counter, the upper four entries of the LUT are all
zero. These entries output the value zero when the counter is reset. Thus, the most
significant bit of the LUT input (
I
3
) represents the reset input (
CLR
) which is
asserted with a logic 1. For the remaining LUT entries, the value at index
I
0..3
of
the LUT contains the value (
I
×
1) modulo 4. To complete the design, the output
signal
O
0..3
must be connected, using the programmable interconnect to the inter-
nal input signal
I
0..3
.
+
O
0..3
From
programmable
interconnect
To
programmable
interconnect
I
0..3
DQ
Addr
Data
Flip-flop
×4
16×4
memory
CK
(a)
Signal Assignment
Addr Data
Addr Data
0
1
4
0
FPGA Counter
I
CLR
1
2
5
0
3
O
2..0
O
2..0
2
3
6
0
CK
CK
3
0
7
0
(b)
Figure 3-33.
(a) A field-programmable logic array lookup table (LUT). (b) The
LUT configuration to create a 3-bit clearable counter.
To better understand the FPGA-based counter with reset, let's consider its op-
eration. If, for example, the current state of the counter is 2 and the reset (
CLR
)
signal is not asserted, the input address to the LUT will be 2, which will produce
an output to the flip-flops of 3. If the reset signal (
CLR
) were asserted for the same
state, the input to the LUT would be 6, which would produce the next state of 0.
