Hardware Reference
In-Depth Information
D
Q
Q
Figure 3-23.
A clocked D latch.
In many circuits it is necessary to sample the value on a certain line at a partic-
ular instant in time and store it. In this variant, called a
flip-flop
, the state tran-
sition occurs not when the clock is 1 but during the clock transition from 0 to 1
(rising edge) or from 1 to 0 (falling edge) instead. Thus, the length of the clock
pulse is unimportant, as long as the transitions occur fast.
For emphasis, we will repeat the difference between a flip-flop and a latch. A
flip-flop is
edge triggered
, whereas a latch is
level triggered
. Be warned, howev-
er, that in the literature these terms are often confused. Many authors use ''flip-
flop'' when they are referring to a latch, and vice versa.
There are various approaches to designing a flip-flop. For example, if there
were some way to generate a very short pulse on the rising edge of the clock sig-
nal, that pulse could be fed into a D latch. There is, in fact, such a way, and the cir-
cuit for it is shown in Fig. 3-24(a).
At first glance, it might appear that the output of the
AND
gate would always be
zero, since the
AND
of any signal with its inverse is zero, but the situation is a bit
more subtle than that. The inverter has a small, but nonzero, propagation delay
through it, and that delay is what makes the circuit work. Suppose that we meas-
ure the voltage at the four measuring points
a
,
b
,
c
, and
d
. The input signal, meas-
ured at
a
, is a long clock pulse, as shown in Fig. 3-24(b) on the bottom. The signal
at
b
is shown above it. Notice that it is both inverted and delayed slightly, typically
hundreds of picoseconds, depending on the kind of inverter used.
The signal at
c
is delayed, too, but only by the signal propagation time (at the
speed of light). If the physical distance between
a
and
c
is, for example, 20
microns, then the propagation delay is 0.0001 nsec, which is certainly negligible
compared to the time for the signal to propagate through the inverter. Thus, for all
intents and purposes, the signal at
c
is as good as identical to the signal at
a
.
When the inputs to the
AND
gate,
b
and
c
, are
AND
ed together, the result is a
short pulse, as shown in Fig. 3-24(b), where the width of the pulse,
, is equal to
the gate delay of the inverter, typically 5 nsec or less. The output of the
AND
gate
is just this pulse shifted by the delay of the
AND
gate, as shown at the top of
Δ
