Hardware Reference
In-Depth Information
S
Q
Clock
Q
R
Figure 3-22. A clocked SR latch.
This circuit has an additional input, the clock, which is normally 0. With the
clock 0, both AND gates output 0, independent of S and R , and the latch does not
change state. When the clock is 1, the effect of the AND gates vanishes and the
latch becomes sensitive to S and R . Despite its name, the clock signal need not be
driven by a clock. The terms enable and strobe are also widely used to mean that
the clock input is 1; that is, the circuit is sensitive to the state of S and R .
Up until now we have carefully swept under the rug the problem of what hap-
pens when both S and R are 1. And for good reason: the circuit becomes nondeter-
ministic when bo t h R and S finally return to 0. The only consistent state for
S
0, but as soon as both inputs return to 0, the latch must jump
to one of its two stable states. If either input drops back to 0 before the other, the
one remaining 1 longest wins, because when just one input is 1, it forces the state.
If both inputs return to 0 simultaneously (which is very unlikely), the latch jumps
to one of its stable states at random.
=
R
=
1is Q
=
Q
=
Clocked D Latches
1) is to
prevent it from occurring. Figure 3-23 gives a latch circuit with only one input, D .
Because the input to the lower AND gate is always the complement of the input to
the upper one, the problem of both inputs being 1 never arises. When D
A good way to resolve the SR latch's instability (caused when S
=
R
=
=
1 and
the clock is 1, the latch is driven into state Q
=
1. When D
=
0 and the clock is 1,
it is driven into state Q
0. In other words, when the clock is 1, the current value
of D is sampled and stored in the latch. This circuit, called a clocked D latch ,isa
true 1-bit memory. The value stored is always available at Q . To load the current
value of D into the memory, a positive pulse is put on the clock line.
This circuit requires 11 transistors. More sophisticated (but less obvious) cir-
cuits can store 1 bit with as few as six transistors. In practice, such designs are
normally used. This circuit can remain stable indefinitely as long as power (not
shown) is applied. Later we will see memory circuits that quickly forget what state
they are in unless constantly ''reminded'' somehow.
=
 
Search WWH ::




Custom Search