Hardware Reference
In-Depth Information
Although a half adder is adequate for summing the low-order bits of two multi-
bit input words, it will not do for a bit position in the middle of the word because it
does not handle the carry into the position from the right. Instead, the
full adder
of Fig. 3-17 is needed. From inspection of the circuit it should be clear that a full
adder is built up from two half adders. The
Sum
output line is 1 if an odd number
of
A
,
B
, and the
Carry in
are 1. The
Carry out
is 1 if either
A
and
B
are both 1 (left
input to the
OR
gate) or exactly one of them is 1 and the
Carry in
bit is also 1. To-
gether the two half adders generate both the sum and the carry bits.
Carry in
Carry
in
Carry
out
A
B
Sum
A
B
Sum
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Carry out
(a)
(b)
Figure 3-17.
(a) Truth table for full adder. (b) Circuit for a full adder.
To build an adder for, say, two 16-bit words, one just replicates the circuit of
Fig. 3-17(b) 16 times. The carry out of a bit is used as the carry into its left neigh-
bor. The carry into the rightmost bit is wired to 0. This type of adder is called a
ripple carry adder
, because in the worst case, adding 1 to 111...111 (binary), the
addition cannot complete until the carry has rippled all the way from the rightmost
bit to the leftmost bit. Adders that do not have this delay, and hence are faster, also
exist and are usually preferred.
As a simple example of a faster adder, consider breaking up a 32-bit adder into
a 16-bit lower half and a 16-bit upper half. When the addition starts, the upper
adder cannot yet get to work because it will not know the carry into it for 16 addi-
tion times.
However, consider this modification to the circuit. Instead of having a single
upper half, give the adder two upper halves in parallel by duplicating the upper
