Hardware Reference
In-Depth Information
(a)
(b)
(c)
Figure 3-10.
Common types of integrated-circuit packages, including a dual-in-
line package (a), pin grid array (b), and land grid array (c).
For our purposes, all gates are ideal in the sense that the output appears as soon
as the input is applied. In reality, chips have a finite
gate delay
, which includes
both the signal propagation time through the chip and the switching time. Typical
delays are 100s of picoseconds to a few nanoseconds.
It is within the current state of the art to put more than 1 billion transistors on a
single chip. Because any circuit can be built up from
NAND
gates, you might think
that a manufacturer could make a very general chip containing 500 million
NAND
gates. Unfortunately, such a chip would need 1,500,000,002 pins. With the stan-
dard pin spacing of 1 millimeter, an LGA would have to be 38 meters on a side to
accommodate all of those pins, which might have a negative effect on sales. Clear-
ly, the only way to take advantage of the technology is to design circuits with a
high gate/pin ratio. In the following sections we will look at simple circuits that
combine a number of gates internally to provide a useful function requiring only a
limited number of external connections (pins).
Many applications of digital logic require a circuit with multiple inputs and
outputs in which the outputs are uniquely determined by the current input values.
Such a circuit is called a
combinational circuit
. Not all circuits have this proper-
ty. For example, a circuit containing memory elements may generate outputs that
depend on the stored values as well as the input variables. A circuit implementing
a truth table, such as that of Fig. 3-3(a), is a typical example of a combinational cir-
cuit. In this section we will examine some frequently used combinational circuits.
Multiplexers
At the digital logic level, a
multiplexer
is a circuit with 2
n
data inputs, one
data output, and
n
control inputs that select one of the data inputs. The selected
data input is ''gated'' (i.e., sent) to the output. Figure 3-11 is a schematic diagram
