SOFTWARE DESIGN VERIFICATION AND VALIDATION - Software Design for Six-Sigma: A Roadmap for Excellence - page 508

FIGURE 19.6 SIL process from dSPACE catalog (Wixom, MI) dSPACE 2008. 8

not available before the end of the architecture design flow, essentially for cost
reasons. The sooner these simulation models are available, the sooner the compilers,
the operating system, and the applications can be designed while meeting a good
integration with the architecture”. 9

19.4.2 Design Verification Process Validation (DVPV) Testing

Design verification process validation (DVPV) testing has become overwhelmingly
reliant on graphic design with simulation tools such MATLABs Simulink, dSPACEs
Targetlink, Simplorer (Wixom, MI), and IBMs Telelogic Statemate (North Castle,
NY) is in part because of their sophistication and versatility and largely in part of
their added functionality of automated code generation. Simulation tools make for
excellent testing tools because they provide instantaneous feedback to system or

8 http://www.dSPACE.de.
9 (www.unisim.org).