SOFTWARE DESIGN VERIFICATION AND VALIDATION - Software Design for Six-Sigma: A Roadmap for Excellence - page 506

19.4.1 The Successive Processes of Model in the Loop (MIL),
Software in the Loop (SIL), Processor in the Loop (PIL), and Hardware
in the Loop (HIL) Testing Approaches
The usefulness of this approach is that in a well-modeled system using the proper
software tools, the software that commands the model can be the same control soft-
ware for microprocessors and microcontrollers in the physical system. This approach
also lends itself to an iterative validation or verification approach in that the custom
hand written software or computer-generated code can be tested at multiple levels and
with several interfaces that progressively approach integration into the final physical
system. This iterative approach commonly is recognized in modern design engineer-
ing as the successive processes of model in the loop (MIL), software in the loop
(SIL), processor in the loop (PIL), and hardware in the loop (HIL) testing.
19.4.1.1 MIL. MIL occurs when model components interface with logical models
for model-level correctness testing. Figure 19.5 shows an example of MIL process
from dSPACE (Wixom, MI). 5
Consider a software system that is ready for testing. Within the same paradigm
that the software itself represents a physical reality, it is reasonable to expect that
a software representation of inputs to the system can achieve the desired validation
results. As the system has been designed and is ready for testing, so can test software
be designed to represent real-world input to the system. A reasonable validation
procedure can be undertaken by replacing inputs with data sources that are expected,
calculable, or otherwise predefined, and monitoring the output for expected results is
an ordinary means of simulating real system behavior.
19.4.1.2 SIL. SIL occurs after code has been generated from a model and run
as an executable file that is configured to interact with the model software. Figure
19.6 shows an example of an SIL process from dSPACE. This midway point in
the V design methodology is perhaps the most important stage of testing, as the
progression will begin at this point to lead into hardware testing. This is the optimal
stage at which code optimization for hardware should be considered and before the
configuration grows in complexity. Code optimization is dependent on the constraints
of the design under test (DUT). For example, it may be necessary to minimize the line
of code count to not exceed read only memory (ROM) limitations based on particular
microprocessor architecture. Other code optimizations can include loop unraveling.
19.4.1.3 PIL. From this point, PIL testing is undertaken for proof that the gener-
ated code can run on a hardware platform such as microcontroller, electrically erasable
programmable read-only memory (E/EE/PROM) or field programmable gate array
(FPGA). Figure 19.7 shows an example of a PIL process from dSPACE.
5 http://www.dSPACE.de.