SOFTWARE OPTIMIZATION TECHNIQUES - Software Design for Six-Sigma: A Roadmap for Excellence - page 445

17.3.2 Interrupt Latency

As discussed in the previous section, interrupt latency is a component of response
time and is the period of time between when a device requests the interrupt and when
the first instruction for the hardware Interrupt Service Routine executes (LaPlante,
2005). In regard to real-time systems, it is important to calculate the worst-case
interrupt latency of a system. Real-time systems usually have to disable interrupts
while the system processes waiting threads.

An interrupt fires only when all of the following conditions are true:
1. The interrupt is pending.
2. The processor's master interrupt enable bit is set.
3. The individual enable bit for the interrupt is set.
4. The processor is in between executing instructions or else is in the middle
of executing an interruptible instruction.
5. No higher priority interrupt meets conditions 1-4 (Regehr, 2008).

Because an interrupt only fires when all five of the conditions are met, all five
factors can contribute to interrupt latency. The worst-case interrupt latency is the
longest possible latency of a system. The worst-case latency usually is determined
by static analysis of an embedded system's object code.
If the embedded system does not react in time, then degradation or failure of
the operating system may occur, depending on whether it is a hard or soft real-time
system. 15 Real-time capability generally is defined by interrupt latency and context
switch time. Interrupts typically are prioritized and are nested. Thus, the latency
of the highest priority interrupt usually is examined. Once the latency is known, it
can be determined whether it is tolerable for a particular application. As a result,
a real-time application will mandate certain maximum latencies to avoid failure or
degradation of the system. If a system's worst-case interrupt latency is less than the
application's maximum tolerable latency, then the design can work. Interrupt latency
may be affected by several factors, including interrupt controllers, interrupt masking,
and the operating system's interrupt handling methods.
In addition to other factors such as context switch time, interrupt latency is proba-
bly the most often analyzed and benchmarked measurement for embedded real-time
systems. 16 Software actually can increase interrupt latency by deferring interrupt
processing during certain types of critical operating system operations. The operat-
ing system does this by disabling interrupts while it performs critical sequences of
instructions. The major component of worst-case interrupt latency is the number and
length of these sequences. If an interrupt occurs during a period of time in which the
operating system has disabled interrupts, then the interrupt will remain pending until
software reenables interrupts which is illustrated in Figure 17.2.

15 http://www.rtcmagazine.com/articles/view/100152
16 http://www.cotsjournalonline.com/articles/view/100129