SOFTWARE DESIGN METHODS AND REPRESENTATIONS - Software Design for Six-Sigma: A Roadmap for Excellence - page 94

variables. It is used to represent high-level concepts in control-flow dominated
systems, and it is mainly suited for synthesis purposes. The model provides an
intermediate format that allows hardware/software designs at the system level
to be synthesized.
Hierarchical Concurrent FSM (HCFSM) (Niemann, 1998) solves the drawbacks
of FSMs by decomposing states into a set of substates. These substates can be
concurrent substates communicating via global variables. Therefore, HCFSMs
supports hierarchy and concurrency. Statecharts is a graphical state machine
language designed to capture the HCFSM MOC (Vahid & Givargis, 2001). The
communication mechanism in statecharts is instantaneous broadcast, where the
receiver proceeds immediately in response to the sender message. The HCFSM
model is suitable for control-oriented/real-time systems.
Codesign FSM (CFSM) (Cortes et al., 2002), (Chiodo et al., 1993) adds concur-
rency and hierarchy to the classic FSM and can be used to model both hardware
and software. It commonly is used for modeling control-flow dominated sys-
tems. The communication primitive between CFSMs is called an event, and the
behavior of the system is defined as sequences of events. CFSMs are used widely
as intermediate forms in codesign systems to map high-level languages, used to
capture specifications, into CFSMs. The Polis codesign system uses CFSM as
its underlying MOC.
4.5.6.2 Discrete-EventSystems. In a discrete-event system, the occurrence of
discrete asynchronous events triggers the transitioning from one state to another. An
event is defined as an instantaneous action and has a time stamp representing when the
event took place. Events are sorted globally according to their time of arrival. A signal
is defined as a set of events, and it is the main method of communication between
processes (Cortes et al., 2002). Discrete-event modeling often is used for hardware
simulation. For example, both Verilog and VHDL use discrete-event modeling as
the underlying MOC (Edwards et al., 1997). Discrete-event modeling is expensive
because it requires sorting all events according to their time stamp.
4.5.6.3 Petri Nets. Petri nets are used widely for modeling systems. Petri nets
consist of places, tokens, and transitions, where tokens are stored in places. Firing a
transition causes tokens to be produced and consumed. Petri nets support concurrency
and are asynchronous; however, they lack the ability to model hierarchy. Therefore,
it can be difficult to use petri nets to model complex systems because of their lack of
hierarchy. Variations of petri nets have been devised to address the lack of hierarchy.
For example, the hierarchical petri nets (HPNs) were proposed by Dittrich (Agrawal,
2002). HPNs support hierarchy in addition to maintaining the major petri net features
such as concurrency and asynchronously. HPNs use Bipartite 28 directed graphs as the
underlying model. HPNs are suitable for modeling complex systems because they
support both concurrency and hierarchy.
28 A graph where the set of vertices can be divided into two disjoint sets U and V such that no edge has
both end points in the same set.