SOFTWARE DESIGN METHODS AND REPRESENTATIONS - Software Design for Six-Sigma: A Roadmap for Excellence - page 91

Cosynthesis : Niemann classifies (Niemann, 1998) several design steps as part
of cosynthesis:

1. Communication synthesis: Implementing the partitioned system on het-
erogeneous target architecture requires interfacing between the ASIC com-
ponents [hardware (HW)] and the processors [software (SW)] communi-
cation between the ASIC(s) and the processors. This is accomplished in
communication synthesis step.
2. Specification refinement: Once the system is partitioned into hardware and
software, and the communication interfaces are defined (via communica-
tion synthesis), the system specification is refined into hardware specifica-
tions and software specifications, which include communication methods
to allow interfacing between the hardware and software components.
3. Hardware synthesis : AISC components are synthesized using behavior
(high-level) synthesis and logic synthesis methods. Hardware synthesis
is a mature field because of the extensive research done in this field.
References (Camposano & Wolf, 1991), (Devadas et al., 1994) provide
details about hardware synthesis methods.
4. Software synthesis : This step is related to generating, from high-level
specification, C or assembly code for the processor(s) that will be executing
the software part of the heterogeneous system. Edwards et al. (1997)
provides an overview of software synthesis techniques.

4.5.4 Validation

Informally, validation is defined as the process of determining that the design, at dif-
ferent levels of abstractions, is correct. The validation of hardware/software systems
is referred to as co-validation . Methods for co-validations are (Edwards et al., 1997;
Domer et al., XXXX).

Formal verification is the process of mathematically checking that the system
behavior satisfies a specific property. Formal verification can be done at the
specification or the implementation level. For example, formal verification can
be used to check the presence of a deadlock condition in the specification model
of a system. At the implementation level, formal verification can be used to check
whether a hardware component correctly implements a given finite state machine
(FSM). For heterogeneous systems (i.e., composed of ASIC components and
software components), formal verification is called coverification .
Simulation validates that a system is functioning as intended by simulating a
small set of inputs. Simulation of heterogeneous embedded systems requires
simulating both hardware and software simultaneously, which is more complex
than simulating hardware or software separately. Simulation of heterogeneous
systems is referred to as cosimulation . A comparison of cosimulation methods
is presented in Camposano and Wolf (1991).