Environmental Engineering Reference
In-Depth Information
Notice in Figure 5.19 that in addition to the normal inverter bridge and its gate
drive and controller, there is a requirement for a second set of controller commands
and gate driver signals for the six thyristors. The distinction at this point is that the
cascade thyristor gates must be driven by fully isolated gate drives. Since thyristors
such as the SCRs shown require only a gate pulse (typically 10 m s) of several
amperes magnitude, a relatively compact isolation transformer and driver transistor
suffice. In operation, the DMIC controller commands the MOSFET bridge gates in
the same fashion as depicted in Figure 5.20, except that when commands A รพ and
A are sent to the MOSFET gates, this same gating signal (leading edge pulse) is
sent to the corresponding thyristor gates, T1 and T2. Once fired, thyristor T1
conducts motor drive current for the positive half cycle (and T2 for negative half
cycle). However, at some point into the conduction of phase A current, the motor
back-emf will equal the supply voltage, and thyristor T1, for example, will then
naturally commutate off and regain its forward and reverse voltage blocking cap-
ability. Once recovered, thyristor T1 will stand off the motor back-emf potential.
The same procedure applies to the remaining phases so that motor braking current
is inhibited, there is no diode conduction, hence no loss of torque and full function
is maintained. In the generating mode, the thyristors must be again gated on to
permit current flow out of the motor phases that is 180 shifted from its motoring
polarity. Under regeneration mode, a conventional thyristor is unable to naturally
commutate off, so operation into field weakening range should be blanked. This is a
disadvantage of the DMIC concept, but not a strict liability, since replacement of
the SCRs with GTOs or other device capable of being force commutated
will provide full 4-quadrant capability to 6:1 CPSR. Also, various ac switches are
under development that would make an excellent match to the DMIC inverter
cascade stage.
The limitations of the DMIC with SCR thyristors are shown in Figure 5.20
with solid and dotted traces for motoring and generating capability curves. Without
the feature of forced commutation, the cascade converter cannot block braking
currents from the SPM motor when its speed is in an overhauling condition. The
SPM back-emf in that case will exceed the bus voltage, and once an SCR is gated
on, there will not be an occasion for natural commutation off during the half cycle
before the 1 pu bridge is into an overvoltage condition. With force commutated
thyristors, the cascade stage is commanded on with gate pulses and commanded off
with negative gate pulses (GTO switch), or ac switches with forward and reverse
voltage blocking capability are used.
The ac switches are capable of bidirectional current conduction and bidirec-
tional voltage blocking. Figure 5.21 illustrates five classes of ac switches that are
available for use in the DMIC inverter. Transistor-based ac switches maintain
conduction while base current or gate voltage persists. Thyristor-based ac switches
conduct after being pulsed on, and conduction is only extinguished when the circuit
current naturally reverses or when the gate electrode is pulsed negative.
There are two disadvantages associated with thyristor ac switches: low
switching speed and turn-off capability. Thyristors are known to have latch-up
problems or commutation failures (GTO). Lack of switching frequency is a major
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