Databases Reference
In-Depth Information
Table 13.1
SMP and NUMA Memory Access Bandwidths
13.3.2 Cache Coherence and False Sharing
The terms “cache coherence” and “false sharing” refer to the consistency of memory in a
server with multiple CPUs. Cache coherency is required to ensure that a data change in
memory performed by one CPU is known by other CPUs, and to ensure that a CPU
modifying a data value in memory cannot do so if the operand is currently being used
by another CPU on the system. Within the CPU, data in the level 1 cache is stored in
rows of data called
cachelines
. Each cacheline is either valid or invalid at a point in time.
If the cacheline is invalid it will need to be reloaded from a higher-level cache or from
RAM. Data is stored in cachelines based on its address in RAM. Therefore, the alloca-
tion of RAM data to specific cachelines is deterministic. Cachelines are typically 128-
512 bytes wide.
False sharing is a related phenomenon where multiple CPUs modify totally dif-
ferent data points (i.e., at different addresses in real memory) that happen to lie on
the same cache line in the level 1 cache of the processor CPU. Because the atomic
unit of cache coherency in modern microprocessors is the cacheline, once the cache-
line of one CPU is invalidated due to an update, the same cacheline on other CPUs
on the server needs to be updated. The synchronization process is terribly inefficient.
The process is called “false sharing” because in fact the memory addresses between an
updater on one CPU and a reader on another CPU were not common—only the
cacheline was common. As parallelism increases on a multiprocessor shared-memory
server, the overhead of cache coherency and the frequency of false sharing also tend to
increase. These phenomena limit the scalability of shared-memory systems under
high concurrency situations.
