Digital Signal Processing Reference
In-Depth Information
It can be shown that an unbounded number of simulation diagrams can be drawn
for a given difference equation. Two standard forms will be given here. We consid-
er some other forms in Chapter 13.
As stated in Section 10.5, with the general form of an
N
th-order linear
difference equation with constant coefficients is
a
0
Z 0,
N
M
[eq(10.48)]
a
k
y[n - k] =
a
b
k
x[n - k].
a
k= 0
k= 0
To introduce the standard forms, a second-order difference equation will be consid-
ered. We will then develop the forms for the
N
th-order equation of (10.48).
For a second-order system, we can express the difference equation as
a
0
y[n] + a
1
y[n - 1] + a
2
y[n - 2] = b
0
x[n] + b
1
x[n - 1] + b
2
x[n - 2].
(10.66)
We denote the right side of this equation as
w[n] = b
0
x[n] + b
1
x[n - 1] + b
2
x[n - 2].
A representation of this equation by a block diagram is shown in Figure 10.14(a).
Then (10.66) becomes
a
0
y[n] + a
1
y[n - 1] + a
2
y[n - 2] = w[n].
Solving for
y
[
n
] yields
1
a
0
y[n] =
[w[n] - a
1
y[n - 1] - a
2
y[n - 2]],
(10.67)
with This equation can be realized by the system of Figure 10.14(b). The
total realization is the cascade (series) connection of the systems in Figure 10.14(a)
and (b), with the result given in Figure 10.14(c). This block diagram realizes (10.66)
and is called the
direct form I
realization.
A second form for realizing a difference equation is now derived by manipu-
lating form I of Figure 10.14(c). The system of this figure is seen to be two systems
in cascade. The first system has the input
x
[
n
] and the output , and the second
system has the input and the output
y
[
n
]. Because the systems are linear, the
order of the two systems can be reversed without affecting the input-output charac-
teristics of the total system. The result is shown in Figure 10.15(a).
Note that in Figure 10.15(a), the same signal is delayed by the two sets of cas-
caded delays; hence, the outputs of the delays labeled “1” are equal, as are the out-
puts of the delays labeled “2.” Therefore, one set of the cascaded delays can be
eliminated. The final system is given in Figure 10.15(b), and we see that only two de-
lays are required. This block diagram is called the
direct form II
realization.
a
0
Z 0.
w[n]
w[n]
