Graphics Reference
In-Depth Information
Main memory
2-way associative cache
way 1
way 2
Figure 13.1
Illustrating how main memory is mapped into a 2-way associative cache.
misses are frequent. A level-2 cache, when present, sits between the level-1 cache
and main memory. When an L1 cache miss occurs, the L2 cache is checked, and only
if it too results in a miss is main memory accessed.
The L2 cache is not as fast as the L1 cache but is quite a bit faster than main memory.
Because the L2 cache is cheaper to manufacture than an L1 cache, its capacity is
larger, usually about 128 KB to 1 MB but potentially higher. A smaller number of
CPUs include a third level of cache memory in their memory hierarchy.
Optimizing for cache utilization means staying on cache as much as possible and
minimizing the number of cache line misses. Cache misses, whether code or data
related, can be categorized into the following three types [Hill89].
●
Capacity misses.
These are caused by there not being enough space in the cache
to hold all active data at the same time. They can be avoided by use of data
compression, rearranging data to be less spread out, and by hot/cold removal
of infrequently accessed data (as discussed in Section 13.3.1, on structure
optimization).
●
Conflict misses.
These correspond to the cache thrashing caused by the number
of accessed memory blocks mapping to the same cache line being greater than
the associativity of the cache. Conflict misses can be avoided by compressing or
rearranging data to not map to the same cache lines.
●
Compulsory misses.
These correspond to the unavoidable misses that take place
when a block of memory is read for the first time. They can be minimized
through increased cache line utilization by putting simultaneously accessed data
together on the same cache line and by using less data or making it smaller.
Additional information on the organization of caches and memory hierarchies
can be found in most introductory topics on computer architecture,
such as
[Hennessy02].
