Digital Signal Processing Reference
In-Depth Information
14.3 Convolutional Coding
Each convolutional coder (Fig. 14.12.) consists of stages with more or less
delay and with memory which, in practice, are implemented by using shift
registers. In DVB-S, and also in DVB-T, it was decided to use a six-stage
shift register with 5 taps each in the upper and lower signal path. The time-
delayed bit streams taken from these taps are Exclusive-ORed with the un-
delayed bit stream and thus result in two output data streams, subjected to
a so-called convolution, each with the same data rate as the input data rate.
A convolution occurs whenever a signal “manipulates” itself, delayed in
time.
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+
out1[ ]
+
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[ ]
o[ ]
n[ ]
o[ ]
n[ ]
in[ ]
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+
out2[ ]
Fig. 14.13.
Sample 2-stage convolutional coder
A digital filter (FIR) also performs a convolution. It would take too
much time to analyse the convolutional coder used in DVB-S and DVB-T
directly since, due to its six stages, it has a memory of 2
6
= 64. Reducing it,
therefore, to a sample encoder having only two stages we only need to
look at 2
2
= 4 states. The shift register can assume the internal states 00,
01, 10 and 11. To test the behaviour of the circuit arrangement it is then
necessary to feed a zero and a one into the shift register for each of these 4
states and then to analyse the resulting state and also to calculate the output
signals due to the Exclusive OR operations. If, e.g., a zero is fed into the
shift register which has a current content of 00, the resultant new content
will also be 00 since one zero is shifted out and at the same time a new
zero is shifted in. In the upper signal path, the two EXOR operations pro-
duce an overall result of 0 at the output. The same applies to the lower
signal path.
If a one is fed into the shift register with contents 00, the new state will
be 10 and a one is obtained as output signal in the upper signal path as well
as in the lower signal path. The other three states can be worked out in the
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