Digital Signal Processing Reference
In-Depth Information
uted, as “unsystematically” as possible. Maximum interleaving is over 11
transport stream packets. The sync bytes and inverted sync bytes always
precisely follow a particular path. This means that the speed of rotation of
the switches corresponds to an exact multiple of the packet length and in-
terleaver and de-interleaver are synchronous with the MPEG-2 transport
stream.
Single
error
Burst error
123456
Deinterleaving in the
receiver
4
2
5
1
3
6
Fig. 14.10.
De-interleaving
The next stage of the modulator is the convolutional coder (trellis
coder). This stage represents the second, so-called inner error protection.
The convolutional coder has a relatively simple structure but understand-
ing it is not quite as simple.
The convolutional coder consists of a 6-stage shift register and two sig-
nal paths in which the input signal is mixed with the content of the shift
register at certain tapping points. The input data stream is split into 3 data
streams. The data first run into the shift register where they influence the
upper and lower data stream of the convolutional coder by an Exclusive
OR operation lasting 6 clock cycles. This disperses the information of one
bit over 6 bits. At specific points both in the upper data branch and in the
lower data branch there are EXOR gates which mix the data streams with
the contents of the shift register. This provides two data streams at the out-
put of the convolutional coder, each of which exhibits the same data rate as
the input signal. In addition, the data stream was only provided with a par-
ticular memory extending over 6 clock cycles. The total output data rate is
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