Hardware Reference
In-Depth Information
The SPE (SPI enable) is required for any SPI communication to take place, and in conjunction with the MSTR
will automatically configure some pin directions as either input or output. Pins that are still user configured must be
set manually. When the MSTR bit is set, the device is in master mode, only forcing MISO to input, so the MOSI, SCK,
and SS should be manually set. If the MSTR is left off, the device is a slave, and all SPI lines except MISO are set as
input. Depending on the nature of the project's code, it may not be necessary to set the MISO as output, in which case
the slave is set to a receive-only mode. This may be useful in a situation where you need to push data or a command
to multiple devices at once but do not need anything returned from the slave. In these cases it may even be possible
to use a single SS line that is common to all devices if the data being sent is the same for all end devices. Otherwise,
the MISO must be set to output on the slave to allow for full-duplex communication. SPI pin modes are outlined in
Table
10-5
for master and slave.
Table 10-5.
SPI Master vs. Slave Pin Modes
Master
Slave
MOSI
User set
Force input
MISO
Force input
User set
SCK
User set
Force input
SS
User set
Force input
Returning to the DORD that was skipped over in the SPCR, this bit controls the order in which the bits of the
SPDR are transmitted. The default setting is 0 and will shift the MSB of the SPDR first and the LSB last. If set to 1, then
the reverse will happen—the LSB will be sent first and the MSB last. It is important that these agree on both the master
and the slave.
CPOL and CPHA on the master device determine how the clock is to be generated, as well as when data is to
be shifted to and from the SPDR. A slave device will use these to control how it responds to the clock signal from
the master. The slave will sample the data line when triggered and set the outgoing bit on clock setup. We saw a full
explanation of the clock modes earlier in the chapter. The CPOL and CPHA settings for each mode are listed Table
10-6
.
Table 10-6.
SPI Clock-Generation Modes
CPOL
CPHA
Mode 0
0
0
Mode 1
0
1
Mode 2
1
0
Mode 3
1
1
The last two bits of the SPCR, SPR1 and SPR0, set the clock divider along with the last bit of the SPSR, SPI2X,
which is a clock multiplier. Setting the SPI2X will double the clock rate; this, combined with the available speeds from
SPR1 and SPR0, yields a range of clock dividers from 2 to 128. It is worth noting again that the Atmel data sheet states
that the minimum clock divider that should be used is 4. In practice, attempting to use a clock divider of 2 should
return corrupt data. The speed settings are listed in Table
10-7
.
