Hardware Reference
In-Depth Information
Serial Peripheral Interface
SPI is almost the same as serial communication, being capable of full-duplex communication while providing
synchronous connection between devices. SPI offers the following advantages:
•
It can achieve very high speeds and is normally implemented between one master and one or
more slaves.
•
There is no clock limit set by the SPI standard, and it is limited only by the hardware's
maximum clock speed.
•
The clock is shared between SPI devices, eliminating the need for the devices to be
individually clocked. The master SPI device controls the clock and is similar to the method
used by I2C.
•
SPI slave devices do not have the ability to temporally hold the clock that is inherent for I2C
devices.
•
SPI has defined a range of connection types: three-wire, which uses a bidirectional data line
(a half-duplex method); the more common four-wire; and five-wire, which adds a data-ready
line to provide the ability for a slave device to inform the master that data needs to be transferred.
Not
■
the lack of defined protocols can be problematic when integrating multiple devices, as each device can
implement unique protocols, possibly making interconnectivity difficult. a router can be used to bridge dissimilar spi
protocols by translating and passing data from one spi network to another. Manufacturer data sheets should contain all
the information needed to develop such a router. the lack of defined protocols is also an advantage in that it provides
flexibility to tailor protocols to the application.
There are a lot of abbreviations used in this chapter, so Table
10-1
acts as a handy reference guide.
Table 10-1.
SPI Abbreviations
Abbreviation
Definition
SCK (serial clock)
The clock signal generated by the SPI master associated with data
transfer
SS (slave select)
A logical high or low signal line used to select one or multiple devices
MOSI (master out slave in)
A shared data line on all SPI devices in a network; this is the output of
the master's shift register and the input of the slave's
MISO (master in slave out)
A shared data line on all SPI devices in a network; this is the input of
the master's shift register and the output of the slave's
CLI (clear interrupts)
Clears the global interrupt enable flag
SEI (set interrupts)
Sets the global interrupt flag
ISR (interrupt service routine)
Used to define event handling on the processor
SPCR (SPI control register)
An 8-bit register that defines a majority of SPI functionality and
configuration
(
continued
)
