Hardware Reference
In-Depth Information
So what about the L2 cache on the Raspberry Pi? It's there in a fashion: Broadcom has assigned the L2 cache
to be used by the GPU; in terms of clock cycles the L2 cache is closer to the GPU than the ARM11 core. In addition,
by dedicating the L2 cache to the GPU you can get more performance from the GPU. The CPU will map requests
around the L2 cache; after all, our main system memory is sitting on top of the SoC so don't be concerned about the
Raspberry Pi mapping around the L2 cache. It's not going to give you any big noticeable performance issues.
No L2 cache has to be bad: will the sky fall? It's hard to compare CPU architectures and how more or less cache
will affect that CPU without understanding that you are comparing apples and oranges. A different CPU architecture
will benefit from more cache whereas in some CPUs the addition of more cache will not give you a lot of notable
benefit. The ARM cores are not starved for data unlike some of the powerful x86 chips. So I urge you to not worry
about the L2 cache; if the ARM1176JZF-S suffered that badly from the lack of an L2 cache ARM would have added one.
The ARM1176JZF-S has a good way of controlling the caches too. It makes use of a dedicated coprocessor to
handle all cache functions. This means that the main integer core can focus more on the task at hand, which is
processing your request and not controlling the cache. This coprocessor also takes care of the main system memory
access. It will control what is in the cache and how the main system memory has been accessed and how each cache
has been accessed as well. Each data path between the caches and main system memory is 64 bits wide, giving the
ARM11 a bit more throughput. This allows more data to flow though each path concurrently.
Memory Chips
On the topic of main system memory, if you take a close look at your Pi board you will notice an absence of a separate
DDR2 memory chip. So where is all of that 256 MB of DDR2 stored?
Surprisingly it's a single chip on top of the SoC chip. The main chip in the center of your Pi is in fact two chips
stacked together like a sandwich but using an array of little conductive metal balls and sockets called a ball grid array
rather than mustard to connect the layers. On the bottom and connected via the ball grid array to the mainboard is
the SoC and stacked on top of that once again via the ball grid array is the 256-MB DDR2 memory chip. This is called
“package on package” and not “sandwich,” though I like sandwich better: it sounds tasty and package on package
sounds boring.
Power States
Lastly I want to talk about the power states of the ARM1176JZF-S. This may be of great interest if you're going to leave
your Raspberry Pi on for long periods of time, say, for example, in Chapter 9 when you will set up the serial server as a
headless remote terminal. You may need the remote terminal only once a month, so why let the core and peripherals
run at full speed and voltage?
The Raspberry Pi has four distinct power modes.
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The first mode should be pretty obvious: it's called the run mode and it means that the CPU
and all functionality of the ARM11 core are available and powered up. This is the default
mode of operation of the core. If you are using your Raspberry Pi for everyday use I would
recommend you stick with this mode because you will need all the power you need.
•
The second sate is the standby mode. In this mode the main core clocks are shut down
although the power circuits on the core are still active. By this, I mean that the parts of the
CPU that process your instructions are no longer running. They are in the same state as if you
were to remove the power from the Raspberry Pi. This makes the core draw less current as it's
not actively running anything, so it's just like a zombie. In this mode the core can be quickly
woken up by a process generating a special call to the CPU called an interrupt. This interrupt
will stop any current processing and do what the calling process has asked for. This mode is
known as Wait for Interrupt, or WFI.
