Digital Signal Processing Reference
In-Depth Information
3.3 Altera Cyclone Architecture - A Look-Up Table FPGA
Device
The Cyclone device is configured by loading internal static random access
memory (SRAM). Since SRAM is used in FPGAs, the configuration will be
lost whenever power is removed. In actual systems, a small external low-cost
serial flash memory or programmable read only memory (PROM) is normally
used to automatically load the FPGA's programming information when the
device powers up.
FPGAs contain a two-dimensional row and column-based architecture to
implement user logic. A column and row interconnection network provides
signal connections between Logic Array Blocks (LABs) and embedded memory
blocks. Interconnect delay times are on the same order of magnitude as logic
delays.
The Cyclone FPGA's logic array consists of LABs, with 10 Logic Elements
(LEs) in each LAB. An LE is a small unit of logic providing efficient
implementation of user logic functions. LABs are grouped into rows and
columns across the device. Cyclone devices range from 2,910 to 20,060 LEs.
M4K RAM embedded memory blocks are dual-port memory blocks with 4K
bits of memory plus parity (4,608 bits). These blocks provide dual-port or
single-port memory from 1 to 36-bits wide at up to 200 MHz. These blocks are
grouped into columns across the device in between certain LABs. The Cyclone
EP1C6 and EP1C12 contain 92K and 239K bits of embedded RAM
respectively.
Each of the Cyclone device's I/O pins is fed by an I/O element (IOE) located at
the ends of LAB rows and columns around the periphery of the device. I/O pins
support various single-ended and differential I/O standards. Each IOE contains
a bidirectional I/O buffer and three registers for registering input, output, and
output-enable signals.
Cyclone devices also provide a global low-skew clock network and up to two
Phase Locked Loops (PLLs). The global clock network consists of eight global
clock lines that drive throughout the entire device. The global clock network
can provide clocks for all resources within the device, such as IOEs, LEs, and
memory blocks. Cyclone PLLs provide general-purpose clocking with clock
multiplication/division and phase shifting as well as external outputs for high-
speed differential I/O support.
Figure 3.7 shows a Cyclone logic element. Logic gates are implemented using
a look-up table (LUT), which is a high-speed 16 by 1 SRAM. Four inputs are
used to address the LUT's memory. The truth table for the desired gate network
is loaded into the LUT's SRAM during programming. A single LUT can
therefore model any network of gates with four inputs and one output. The
multiplexers seen in Figure 3.7 are all controlled by bits in the FPGA's SRAM
configuration memory.
